MPC8260A Motorola, MPC8260A Datasheet - Page 3

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MPC8260A

Manufacturer Part Number
MPC8260A
Description
Micro Processor
Manufacturer
Motorola
Datasheet

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Figure 1 shows the block diagram for the HiP4 superset device, the MPC8266A.
1.1
The major features of the MPC826xA family are as follows:
MOTOROLA
MCC1
Parallel I/O
Generators
Baud Rate
Timers
MCC2
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–300 MHz
— Separate 16-Kbyte data and instruction caches:
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (6.6–7.65 SPEC95 benchmark at 300 MHz; 420 Dhrystones MIPS at
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
Separate power supply for internal logic and for I/O
G2 Core
Features
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
300 MHz)
Communication Processor Module (CPM)
FCC1
TC Layer Hardware
8 TDM Ports
Interrupt
Controller
32-bit RISC Microcontroller
FCC2
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
and Program ROM
MPC826xA (HiP4) Family Hardware Specifications
FCC3
1,3
16 Kbytes
16 Kbytes
D-Cache
I-Cache
D-MMU
I-MMU
Dual-Port RAM
SCC1
Figure 1. MPC8266A Block Diagram
32 Kbytes
Microcode
IMA
SCC2
1,3
SCC3
Time Slot Assigner
3 MII
Ports
Serial Interface
4 Virtual
DMAs
Serial
IDMAs
SCC4
SMC1
2 UTOPIA
Ports
System Interface Unit
SMC2
Memory Controller
Bus Interface Unit
System Functions
Clock Counter
60x-to-Local
60x-to-PCI
Bridge
Bridge
(SIU)
Non-Multiplexed
SPI
2,3
I/O
I
2
C
32 bits, up to 66 MHz
32 bits, up to 83 MHz
60x Bus
Notes:
1. MPC8264A
2. MPC8265A
3. MPC8266A
PCI Bus
Local Bus
Features
or
2,3
3

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