PIC12F639 Microchip Technology, PIC12F639 Datasheet - Page 107

• Manufacturer Part Number: PIC12F639
• Description: (PIC12F635 / PIC12F636 / PIC12F639) 8/14-PIN FLASH-BASED / 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY
• Manufacturer: Microchip Technology

TABLE 11-6:
REGISTER 11-1:
© 2005 Microchip Technology Inc.
Configuration Register 0
Configuration Register 1
Configuration Register 2
Configuration Register 3
Configuration Register 4
Configuration Register 5 AUTOCHSEL AGCSIG
Column Parity Register 6
AFE Status Register 7
bit 8-7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Register Name
bit 8
OEH<1:0>: Output Enable Filter High Time (T
00 = Output Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA)
01 = 1 ms
10 = 2 ms
11 = 4 ms
OEL<1:0>: Output Enable Filter Low Time (T
00 = 1 ms
01 = 1 ms
10 = 2 ms
11 = 4 ms
ALRTIND: ALERT bit, output triggered by:
1 = Parity error and/or expired Alarm timer (receiving noise, see Section 11.14.3 “Alarm Timer”)
0 = Parity error
LCZEN: LCZ Enable bit
1 = Disabled
0 = Enabled
LCYEN: LCY Enable bit
1 = Disabled
0 = Enabled
LCXEN: LCX Enable bit
1 = Disabled
0 = Enabled
R0PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Legend:
R = Readable bit
- n = Value at POR
R/W-0
OEH1
ANALOG FRONT-END CONFIGURATION REGISTERS SUMMARY
CONFIGURATION REGISTER 0 (ADDRESS: 0000)
RSSIFET
R/W-0
OEH0
Bit 8
Unimplemented
Active Channel Indicators
DATOUT
Channel X Sensitivity Control
OEH
W = Writable bit
‘1’ = Bit is set
CLKDIV
R/W-0
OEL1
Bit 7
MODMIN MODMIN
PIC12F635/PIC16F636/639
R/W-0
Bit 6
OEL0
Preliminary
OEL
OEH
OEL
) bit
) bit
Column Parity Bits
AGCACT
Bit 5
ALRTIND
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Channel X Tuning Capacitor
Channel Y Tuning Capacitor
Channel Z Tuning Capacitor
ALRTIND
Wake-up Channel Indicators
Bit 4
LCZEN
R/W-0
Channel Y Sensitivity Control
Channel Z Sensitivity Control
LCZEN
Bit 3
LCYEN
R/W-0
LCYEN
Bit 2
x = Bit is unknown
LCXEN
R/W-0
DS41232B-page 105
ALARM
LCXEN
Bit 1
R0PAR
R/W-0
R0PAR
R1PAR
R2PAR
R3PAR
R4PAR
R5PAR
R6PAR
Bit 0
PEI
bit 0