PIC12F639 Microchip Technology, PIC12F639 Datasheet - Page 56

• Manufacturer Part Number: PIC12F639
• Description: (PIC12F635 / PIC12F636 / PIC12F639) 8/14-PIN FLASH-BASED / 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY
• Manufacturer: Microchip Technology

PIC12F635/PIC16F636/639
5.3
When no prescaler is used, the external clock input is the
same as the prescaler output. The synchronization of
T0CKI, with the internal phase clocks, is accomplished
by sampling the prescaler output on the Q2 and Q4
cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 T
small RC delay of 20 ns) and low for at least 2 T
a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
REGISTER 5-1:
DS41232B-page 54
Note:
Using Timer0 with an External
Clock
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
The CMCON0 (19h) register must be ini-
tialized to configure an analog channel as
a digital input. Pins configured as analog
inputs will read ‘0’.
OPTION_REG – OPTION REGISTER (ADDRESS: 81h)
bit 7
RAPU: PORTA Pull-up Enable bit
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual values in the WPUDA register
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RA2/T0CKI/INT/C1OUT pin
0 = Interrupt on falling edge of RA2/T0CKI/INT/C1OUT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA2/T0CKI/INT/C1OUT pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/T0CKI/INT/C1OUT pin
0 = Increment on low-to-high transition on RA2/T0CKI/INT/C1OUT pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Legend:
R = Readable bit
- n = Value at POR
Bit Value TMR0 Rate WDT Rate
R/W-1
RAPU
Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F635/PIC16F636/639.
000
001
010
011
100
101
110
111
See Section 12.11 “Watchdog Timer (WDT)” for more information.
INTEDG
R/W-1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
OSC
OSC
(and a
R/W-1
T0CS
(and
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Preliminary
W = Writable bit
‘1’ = Bit is set
(1)
R/W-1
T0SE
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PSA
R/W-1
PS2
© 2005 Microchip Technology Inc.
x = Bit is unknown
R/W-1
PS1
R/W-1
PS0
bit 0