PIC12F639 Microchip Technology, PIC12F639 Datasheet - Page 44

• Manufacturer Part Number: PIC12F639
• Description: (PIC12F635 / PIC12F636 / PIC12F639) 8/14-PIN FLASH-BASED / 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY
• Manufacturer: Microchip Technology

PIC12F635/PIC16F636/639
4.2.2
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits, IOCAx, enable
or disable the interrupt function for each pin. Refer to
Register 4-5. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (RAIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a)
b)
REGISTER 4-5:
DS41232B-page 42
Any read or write of PORTA. This will end the
mismatch condition, then
Clear the flag bit RAIF.
bit 7-6
bit 5-0
INTERRUPT-ON-CHANGE
IOCA – INTERRUPT-ON-CHANGE PORTA REGISTER (ADDRESS: 96h)
bit 7
Unimplemented: Read as ‘0’
IOCA<5:0>: Interrupt-on-change PORTA Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Legend:
R = Readable bit
- n = Value at POR
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be
U-0
—
2: IOCA<5:4> always reads ‘0’ in XT, HS and LP Oscillator modes.
3: IOCA<3> is ignored when WUR is enabled and the device is in Sleep mode.
recognized.
U-0
—
IOCA5
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
(2)
(1)
IOCA4
R/W-0
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOD
Reset. After these Resets, the RAIF flag will continue
to be set if a mismatch is present.
Note:
(2)
IOCA3
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
(2,3)
(3)
IOCA2
R/W-0
© 2005 Microchip Technology Inc.
x = Bit is unknown
IOCA1
R/W-0
IOCA0
R/W-0
bit 0