MT9075B Mitel Networks Corporation, MT9075B Datasheet - Page 34

• Manufacturer Part Number: MT9075B
• Description: E1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9075B
34
Table 20 - National Use Bit Interrupt Mask Word
Bit
7
6
5
4
3
2
1
0
PRBSO
C8S
PRBSI
Name
S
S
S
S
a
(0)
(0)
(0)
(0)
(0)
(0)
(0)
a
---
nibI
a6
a5
bitI
a6
I
I
(Page 01H, Address 19H)
I
Unused.
PRBS
Interrupt.
(PRBSO = 1), an interrupt is
initiated on overflow of PRBS
counter (page 04H, address 10H)
from FFH to 0H. Interrupt vector =
00000010.
PRBS Interrupt. When unmasked
(PRBSI = 1), an interrupt is initiated
on a single PRBS detection error.
Interrupt vector = 00000010.
Changed S
When unmasked (S
interrupt
detection of a change of state in any
of received S
nibble S
Interrupt vector = 00000010.
Changed S
unmasked (S
is generated upon detection of a
change of state in any of received
S
Interrupt vector = 00000010.
Eight Consecutive S
Interrupt. When unmasked (C8S
= 1), an interrupt is generated upon
detection of the eighth consecutive
S
Interrupt vector = 00000010.
Changed S
When unmasked (S
interrupt
detection of a change of state in
received
vector = 00000010.
Changed S
unmasked (S
generated upon detection of a
change of state in the received S
bit. Interrupt vector = 00000010.
a
a6
bits (S
nibble with the same pattern.
a6
Functional Description
, nibble S
S
a5
is
is
Counter
a5
a
a6
a6
a
a
a5
a
, S
bitI = 1), an interrupt
Bit Interrupt. When
When
Bit Interrupt. When
I =1), an interrupt is
nibbles (nibble S
Nibble Interrupt.
generated
Nibble Interrupt.
generated
nibbles.
a6
a7
, S
a
or nibble S
a6
nibI = 1), an
a7
I = 1), an
a6
unmasked
Overflow
or S
Interrupt
Nibble
upon
upon
a8
a8
a5
a6
a5
).
).
,
I
Bit
7
6
5
4
3
Table 21 - Interrupt, Signalling and BERT
Control Word (Page 01H, Address 1AH)
TxCCS
RPSIG
Name
SPND
INTA
ODE
(0)
(0)
(0)
(0)
(0)
Output Data Enable. If one, the
DSTo and CSTo output drivers
function normally. When low, DSTo
and CSTo will be tristated.
Note: When ODE =1, DSTo and
CSTo can be individually tristated
by DSToDE and CSToDE (page
01H, address 16H) respectively.
Suspend Interrupts. If one, the
IRQ output (pin 12 in PLCC, 85 in
MQFP) will be in a high-impedance
state and all interrupts will be
ignored. If zero, the IRQ output will
function normally.
Interrupt Acknowledge. A zero-to-
one or one-to-zero transition will
clear any pending interrupt and
make IRQ high.
Transmit
Signalling. If one, the transmit
section of the device is in common
channel signalling (CCS) mode. If
zero, it is in Channel Associated
Signalling (CAS) mode.
Register
Signalling. If one, the transmit CAS
signalling will be controlled by
programming page 05H. If zero, the
transmit CAS signalling will be
controlled through the CSTi stream.
(continued)
Preliminary Information
Functional Description
Common
Programmed
Channel