MT9075B Mitel Networks Corporation, MT9075B Datasheet - Page 63

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MT9075B

Manufacturer Part Number
MT9075B
Description
E1 Single Chip Transceiver
Manufacturer
Mitel Networks Corporation
Datasheet

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Preliminary Information
7 - 4
Bit
3
2
1
0
Name
Vaddr
RXclk
Table 96 - HDLC Test Status Register
TXclk
(Page 0BH & 0CH, Address 1CH)
RSV
Vcrc
These bits are reserved.
This bit represents the receiver
clock generated after the RXEN
control bit is enabled, but before
zero deletion is considered.
This bit represents the transmit
clock generated after the TXEN
control bit is enabled, but before
zero insertion is considered.
This is the CRC recognition status
bit for the receiver. Data is clocked
into the register and then this bit is
monitored to see if comparison was
successful (bit will be one).
This is the address recognition
status bit for the receiver. Data is
clocked
Recognition Register and then this
bit is monitored to see if comparison
was successful (bit will be one).
Functional Description
into
the
Address
6 - 4 RFD2 - 0
2 - 0 TFD2 - 0
Bit
7
3
Name
Table 97 - HDLC Control Register 3
(000)
(000)
(Pages 0BH & 0CH, Address 1DH)
---
---
Unused.
These bits select the Rx FIFO full
status level:
RFD2 RFD1 RFD0
Unused.
These bits select the Tx HDLC
FIFO full status level:
TFD2 TFD1 TFD0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Functional Description
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MT9075B
Full Status
Full Status
Level
Level
112
128
112
128
16
32
48
64
80
96
16
32
48
64
80
96
63

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