MT9075B Mitel Networks Corporation, MT9075B Datasheet - Page 58

• Manufacturer Part Number: MT9075B
• Description: E1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9075B
58
Table 83 - HDLC Address Recognition Register1
7 - 2
7 - 1
Bit
Bit
Table 84 - HDLC Address Recognition Register 2
1
0
0
(000000)
(000000)
Name
Adr16
Adr11
Adr10
Name
A1en
(Page 0BH & 0CH, Address 10H)
Ad26
Ad20
A2en
(Pages 0BH & 0CH, Address 11H)
(0)
(0)
(0)
-
-
A six bit mask used to interrogate
the first byte of the received
address. Adr16 is the MSB.
This
comparison, if control bit Seven, bit
4 of HDLC Control Register 2
(address 15H) is one.
When this bit is high, this six (or
seven) bit mask is used in address
comparison of the first address
byte.
If address recognition is enabled,
any packet failing the address
comparison will not be stored in the
RX FIFO. A1en must be high for All-
call (1111111) address recognition
for single byte address. When this
bit is low, this bit mask is ignored in
address comparison
A
interrogate the second byte of the
received address. Adr26 is MSB.
This mask is ignored (as well as first
byte mask) if all call address
(1111111) is received.
When this bit is one, this seven bit
mask
comparison of the second address
byte.
If address recognition is enabled,
any packet failing the address
comparison will not be stored in the
Rx FIFO. A2en must be one for All-
call address recognition. When this
bit is zero, this bit mask is ignored in
address comparison
seven
Functional Description
Functional Description
bit
is
is
bit
used
used
mask
in
in
used
address
address
to
7 - 0
7 - 0
Bit
Bit
Name
Name
Bit7
Bit0
Bit7
Bit0
(Pages 0BH & 0CH, Address 12H)
Table 86 - RX FIFO Read Register
(Pages 0BH & 0CH, Address 12H)
Table 85 - TX FIFO Write Register
-
-
This eight bit word is tagged with
the two status bits (EOP and FA)
from the Control Register 1, and the
resulting 10 bit word is written to the
TX FIFO. The FIFO status is not
changed immediately after a write
or read occurs. It is updated after
the data and the read/write pointers
have settled.
This is the received data byte read
from the RX FIFO. The status bits of
this byte can be read from the
status register. The FIFO status is
not changed immediately when a
write or read occurs. It is updated
after the data and the read/write
pointers have settled.
Preliminary Information
Functional Description
Functional Description