ISLA112P50 Intersil, ISLA112P50 Datasheet - Page 16

• Manufacturer Part Number: ISLA112P50
• Description: 500MSPS A/D Converter
• Manufacturer: Intersil

Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as
shown in Figures 30 through 32. An RF transformer will
give the best noise and distortion performance for
wideband and/or high intermediate frequency (IF)
inputs. Two different transformer input schemes are
shown in Figures 30 and 31.
This dual transformer scheme is used to improve
common-mode rejection, which keeps the
common-mode level of the input matched to VCM. The
value of the shunt resistor should be determined based
on the desired load impedance. The differential input
resistance of the ISLA112P50 is 500Ω.
The SHA design uses a switched capacitor input stage
(see Figure 47), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance
will result in faster settling and improved performance.
Therefore a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier, as shown in Figure 32, can be
used in applications that require DC-coupling. In this
FIGURE 30. TRANSFORMER INPUT FOR GENERAL
FIGURE 31. TRANSMISSION-LINE TRANSFORMER
1000pF
49.9O
0.22µF
FIGURE 32. DIFFERENTIAL AMPLIFIER INPUT
1000pF
1000pF
Ω
ADT1-1WT
69.8O
69.8O
ADTL1-12
PURPOSE APPLICATIONS
INPUT FOR HIGH IF APPLICATIONS
Ω
100O
100O
Ω
Ω
Ω
ADTL1-12
ADT1-1WT
348O
348O
16
CM
Ω
Ω
0.1µF
0.1µF
25O
25O
0.1µF
Ω
Ω
217O
Ω
VCM
A/D
ISLA112P50
VCM
VCM
A/D
A/D
configuration, the amplifier will typically dominate the
achievable SNR and distortion performance.
Clock Input
The clock input circuit is a differential pair (see
Figure 48). Driving these inputs with a high level (up to
1.8V
the lowest jitter performance. A transformer with 4:1
impedance ratio will provide increased drive levels. The
clock input is functional with AC-coupled LVDS, LVPECL,
and CML drive levels. To maintain the lowest possible
aperture jitter, it is recommended to have high slew rate
at the zero crossing of the differential clock input signal.
The recommended drive circuit is shown in Figure 33. A
duty range of 40% to 60% is acceptable. The clock can
be driven single-ended, but this will reduce the edge rate
and may impact SNR performance. The clock inputs are
internally self-biased to AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series
with the clock input. The divider can be used in the 2X
mode with a sample clock equal to twice the desired
sample rate. This allows the use of the Phase Slip
feature, which enables synchronization of multiple A/Ds.
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 22.
Jitter
In a sampled data system, clock jitter directly impacts
the achievable SNR performance. The theoretical
relationship between clock jitter (t
Equation 1 and is illustrated in Figure 34.
SNR
AVDD
P-P
200pF
=
FIGURE 33. RECOMMENDED CLOCK DRIVE
CLKDIV PIN
on each input) sine or square wave will provide
20 log
AVDD
AVSS
TABLE 1. CLKDIV PIN SETTINGS
Float
10
1kO
TC4-1W
⎛
⎝
Ω
------------------- -
2πf
1
IN
t
J
⎞
⎠
1000pF
1kO
Ω
J
) and SNR is shown in
DIVIDE RATIO
Not Allowed
www.DataSheet4U.com
200pF
200pF
200O
2
1
Ω
March 30, 2010
(EQ. 1)
FN7604.0
CLKP
CLKN