ISLA112P50 Intersil, ISLA112P50 Datasheet - Page 23

• Manufacturer Part Number: ISLA112P50
• Description: 500MSPS A/D Converter
• Manufacturer: Intersil

The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command;
SCLK must be static low before the CSB transition. Data
can be presented in MSB-first order or LSB-first order.
The default is MSB-first, but this can be changed by
setting 0x00[6] high. Figures 39 and 40 show the
appropriate bit ordering for the MSB-first and LSB-first
modes, respectively. In MSB-first mode, the address is
incremented for multi-byte transfers, while in LSB-first
mode it’s decremented.
In the default mode, the MSB is R/W, which determines if
the data is to be read (active high) or written. The next
two bits, W1 and W0, determine the number of data
bytes to be read or written (see Table 6). The lower 13
bits contain the first address for the data transfer. This
relationship is illustrated in Figure 41, and timing values
are given in “Switching Specifications” on page 9.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read
from the A/D (based on the R/W bit status). The data
transfer will continue as long as CSB remains low and
SCLK is active. Stalling of the CSB pin is allowed at any
byte boundary (instruction/address or data) if the
number of bytes being transferred is three or less. For
transfers of four bytes or more, CSB is allowed to stall in
the middle of the instruction/address bytes or before the
first data byte. If CSB transitions to a high state after
that point the state machine will reset and terminate the
data transfer.
Figures 43 and 44 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation
for a 3-byte transfer can be inferred from these
diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register.
Bit order can be selected as MSB to LSB (MSB first) or
LSB to MSB (LSB first) to accommodate various micro
controllers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret
serial data as arriving in LSB to MSB order.
TABLE 6. BYTE TRANSFER SELECTION
[W1:W0]
00
01
10
11
23
BYTES TRANSFERRED
4 or more
1
2
3
ISLA112P50
Bit 5 Soft Reset
Bit 4 Reserved
Bits 3:0 These bits should always mirror bits 4:7 to
avoid ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redundant
addressing. In 3-wire SPI mode, the burst is ended by
pulling the CSB pin high. If the device is operated in
2-wire mode the CSB pin is not available. In that case,
setting the burst_end address determines the end of the
transfer. During a write operation, the user must be
cautious to transmit the correct number of bytes based
on the starting and ending addresses.
Bits 7:0 Burst End Address
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number,
respectively, can be read from these two registers.
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A
Bits 1:0 ADC01, ADC00
A common SPI map, which can accommodate
single-channel or multi-channel devices, is used for all
Intersil A/D products. Certain configuration commands
(identified as Indexed in the SPI map) can be executed
on a per-converter basis. This register determines which
converter is being addressed for an Indexed command. It
is important to note that only a single converter can be
addressed at a time.
This register defaults to 00h, indicating that no A/D is
addressed. Error code ‘AD’ is returned if any indexed
register is read from without properly setting
device_index_A.
ADDRESS 0X20: OFFSET_COARSE
ADDRESS 0X21: OFFSET_FINE
The input offset of the A/D core can be adjusted in fine
and coarse steps. Both adjustments are made via an
8-bit word as detailed in Table 7. The data format is twos
complement.
Setting this bit high resets all SPI registers to default
values.
This bit should always be set high.
This register value determines the ending address of
the burst data.
Determines which A/D is addressed. Valid states for
this register are 0x01 or 0x10. The two A/D cores
cannot be adjusted concurrently.
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March 30, 2010
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