ISLA112P50 Intersil, ISLA112P50 Datasheet - Page 21

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ISLA112P50

Manufacturer Part Number
ISLA112P50
Description
500MSPS A/D Converter
Manufacturer
Intersil
Datasheet
SCLK
SDIO
SCLK
SDIO
CSB
CSB
CSB
SDIO
SCLK
R/W
A0
t
S
R/W
t
FPGA or ASIC
DSW
timed signal
with respect
21
W1
to 1GHz
A1
Poorly
W1
Sample
(1GHz)
Clock
W0
W0
A2
A12
t
A12
A11
DHW
FIGURE 38. SYNCHRONIZATION SCHEME
Fan-out
Buffer
FIGURE 39. MSB-FIRST ADDRESSING
FIGURE 40. LSB-FIRST ADDRESSING
Synchronizer
A11
t
HI
A11
A12
A10
DQ Flip Flop Bank
FIGURE 41. SPI WRITE
(EP451, etc)
t
A10
LO
W0
ISLA112P50
A9
D Q
D Q
D Q
D Q
D Q
D Q
t
CLK
SPI WRITE
A1
W1
A8
Delay =
Delay =
R/W
A7
500ps
500ps
A0
D7
D0
D5
D6
D1
D4
D5
D2
SYNC
SYNC
D3
D4
D3
D2
D1
D3
D4
D0
SYNC
SYNC
D2
t
D5
H
www.DataSheet4U.com
D1
D6
D0
D7
March 30, 2010
FN7604.0

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