ISLA112P50 Intersil, ISLA112P50 Datasheet - Page 27

• Manufacturer Part Number: ISLA112P50
• Description: 500MSPS A/D Converter
• Manufacturer: Intersil

ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
ISLA112P50 can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects the
mode and drive level (refer to “Digital Outputs” on
page 17). This functionality can be overridden and
controlled through the SPI, as shown in Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to
“Data Format” on page 18). This functionality can be
overridden and controlled through the SPI, as shown in
Table 14.
This register is not changed by a Soft Reset.
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default)
or slow.
TABLE 12. CLOCK DIVIDER SELECTION
TABLE 14. OUTPUT FORMAT CONTROL
TABLE 13. OUTPUT MODE CONTROL
VALUE
VALUE
VALUE
000
001
010
100
000
001
010
100
000
001
010
100
27
OUTPUT FORMAT
Two’s Complement
CLOCK DIVIDER
OUTPUT MODE
Offset Binary
Not Allowed
0x72[2:0]
Divide by 1
Divide by 2
0x93[2:0]
Pin Control
Pin Control
Gray Code
0x93[7:5]
Pin Control
LVDS 2mA
LVDS 3mA
LVCMOS
ISLA112P50
Internal clock signals are generated by a delay-locked
loop (DLL), which has a finite operating range. Table 15
shows the allowable sample rate ranges for the slow and
fast settings.
The output_mode_B and config_status registers are used
in conjunction to enable DDR mode and select the
frequency range of the DLL clock generator. The method
of setting these options is different from the other
registers.
The procedure for setting output_mode_B is shown in
Figure 46. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that XOR
result to the register.
Device Test
The ISLA112P50 can produce preset or user defined
patterns on the digital outputs to facilitate in-situ testing.
A static word can be placed on the output bus, or two
different words can alternate. In the alternate mode, the
values defined as Word 1 and Word 2 (as shown in
Table 16) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the
sample clock, therefore several sample clock cycles may
elapse before the data is present on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
The four LSBs in this register (Output Test Mode)
determine the test pattern in combination with registers
0xC2 through 0xC5. Refer to “SPI Memory Map” on
page 29.
DLL RANGE
OUTPUT_MODE_B
CONFIG_STATUS
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are reserved.
FIGURE 46. SETTING OUTPUT_MODE_B REGISTER
Slow
Fast
READ
READ
0x74
0x75
TABLE 15. DLL RANGES
DESIRED
MIN
VALUE
160
80
MAX
200
500
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WRITE TO
March 30, 2010
UNIT
MSPS
MSPS
0x74
FN7604.0