ISLA112P50 Intersil, ISLA112P50 Datasheet - Page 22

• Manufacturer Part Number: ISLA112P50
• Description: 500MSPS A/D Converter
• Manufacturer: Intersil

Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to
facilitate configuration of the device and to optimize
performance. The SPI bus consists of chip select (CSB),
serial clock (SCLK) serial data output (SDO), and serial
data input/output (SDIO). The maximum SCLK rate is
equal to the A/D sample rate (f
for write operations and f
reads. At f
15.63MHz for writing and 3.79MHz for read operations.
There is no minimum SCLK rate.
The following sections describe various registers that
are used to configure the SPI or adjust performance or
functional parameters. Many registers in the available
address space (0x00 to 0xFF) are not defined in this
document. Additionally, within a defined register there
may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values
within defined registers are reserved and should not be
selected. Setting any reserved register or value may
produce indeterminate results.
SCLK
SDIO
SCLK
SDIO
CSB
CSB
SAMPLE
CSB
SCLK
SDIO
SDO
= 250MHz, maximum SCLK is
t
S
R/W
INSTRUCTION/ADDRESS
INSTRUCTION/ADDRESS
t
DSW
SAMPLE
22
W1
W0
SAMPLE
divided by 132 for
A12
t
DHW
WRITING A READ COMMAND
) divided by 32
A11
t
HI
FIGURE 44. N-BYTE TRANSFER
FIGURE 43. 2-BYTE TRANSFER
A10
t
FIGURE 42. SPI READ
LO
ISLA112P50
A9
t
CLK
A2
CSB STALLING
SPI READ
DATA WORD 1
CSB STALLING
LAST LEGAL
A1
t
DATA WORD 1
DVR
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for
the data transfer. By default, all data is presented on the
serial data input/output (SDIO) pin in three-wire mode.
The state of the SDIO pin is set automatically in the
communication protocol (described in the following). A
dedicated serial data output pin (SDO) can be activated
by setting 0x00[7] high to allow operation in four-wire
mode.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA112P50 functioning as a
slave. Multiple slave devices can interface to a single
master in three-wire mode only, since the SDO output of
an unaddressed device is asserted in four wire mode.
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in three-wire
mode). If multiple slave devices are selected for reading
at the same time, the results will be indeterminate.
A0
READING DATA
D7
D7
D6
D3
(4 WIRE MODE)
D3
(3 WIRE MODE)
D2
D2
t
DHR
D1 D0
D1
t
DATA WORD N
DATA WORD 2
H
D0
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March 30, 2010
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