ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 100

• Manufacturer Part Number: ST72F264G
• Description: (ST72F260G - ST72F264G) 8-BIT MCU
• Manufacturer: ST Microelectronics

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ST72260G, ST72262G, ST72264G
I
Acknowledge may be enabled and disabled by
software.
The I
dress can be selected by software.
The speed of the I
between Standard (0-100KHz) and Fast I
400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 58. I
100/171
2
C BUS INTERFACE (Cont’d)
SCL or SCLI
SDA or SDAI
4
2
U
C interface address and/or general call ad-
.com
2
C Interface Block Diagram
2
C interface may be selected
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
DATA CONTROL
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL REGISTER (CR)
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2
C (100-
The SCL frequency (F
grammable clock divider which depends on the
I
When the I
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
When the I
ports revert to being standard I/O port pins.
2
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
C bus mode.
DATA SHIFT REGISTER
DATA REGISTER (DR)
CONTROL LOGIC
COMPARATOR
INTERRUPT
2
2
C cell is disabled, the SDA and SCL
C cell is enabled, the SDA and SCL
scl
) is controlled by a pro-
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