ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 18

• Manufacturer Part Number: ST72F264G
• Description: (ST72F260G - ST72F264G) 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
ST72260G, ST72262G, ST72264G
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
Bit 4 = H Half carry .
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Bit 2 = N Negative .
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
sult 7
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
This bit is accessed by the JRMI and JRPL instruc-
tions.
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(i.e. the most significant bit is a logic 1).
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I1
H
I0
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Z
C
0
Bit 1 = Z Zero .
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more
details.
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
zero.
Interrupt Software Priority
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I1
1
0
0
1
I0
0
1
0
1
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