ST72F264G ST Microelectronics, ST72F264G Datasheet - Page 113

• Manufacturer Part Number: ST72F264G
• Description: (ST72F260G - ST72F264G) 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.7.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
If the input voltage (V
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
R
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.7.3.3 A/D Conversion
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the ADCCSR register:
– Select the CH[2:0] bits to assign the analog
ADC Conversion mode
In the ADCCSR register:
- Set the SPEED or the SLOW bits
– Set the ADON bit to enable the A/D converter
AIN
channel to convert.
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
4
is the maximum recommended impedance
U
.com
AIN
AIN
) is lower than V
) is greater than V
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SSA
(low-
DDA
When a conversion is complete:
A read to the ADCDRH or a write to any bit of the
ADCCSR resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRL. This locks the ADCDRH until it
3. Read ADCDRH. This clears EOC automati-
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRH. This clears EOC automati-
11.7.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
11.7.5 Interrupts
None.
Mode
WAIT
HALT
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
is read.
cally.
cally.
ST72260G, ST72262G, ST72264G
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
t
before accurate conversions can be
performed.
STAB
(see Electrical Characteristics)
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