FLLXT971A Intel, FLLXT971A Datasheet - Page 16

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
2.0
16
Table 2.
Note: Intel recommends that all inputs and multi-function pins be tied to the inactive states and all
Signal Descriptions
outputs be left floating, if unused.
LXT971A MII Signal Descriptions
PBGA
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
Pin#
C4
C5
D6
C8
A3
B3
A4
B4
B8
A8
A7
A5
B5
B6
B2
A2
LQFP
Pin#
60
59
58
57
56
55
45
46
47
48
49
53
54
52
62
63
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_ER
TX_ER
RX_CLK
COL
CRS
Symbol
Type
O
O
O
O
O
O
O
I
I
I
1
Transmit Data. TXD is a bundle of parallel data signals that are
driven by the MAC. TXD<3:0> transitions synchronously with
respect to the TX_CLK. TXD<0> is the least significant bit.
Transmit Enable. The MAC asserts this signal when it drives valid
data on TXD. This signal must be synchronized to TX_CLK.
Transmit Clock. TX_CLK is sourced by the PHY in both 10 and
100 Mbps operations.
2.5 MHz for 10 Mbps operation, 25 MHz for 100 Mbps operation.
Receive Data. RXD is a bundle of parallel signals that transition
synchronously with respect to the RX_CLK. RXD<0> is the least
significant bit.
Receive Data Valid. The LXT971A asserts this signal when it drives
valid data on RXD. This output is synchronous to RX_CLK.
Receive Error. Signals a receive error condition has occurred.
This output is synchronous to RX_CLK.
Transmit Error. Signals a transmit error condition. This signal must
be synchronized to TX_CLK.
Receive Clock. 25 MHz for 100 Mbps operation, 2.5 MHz for
10 Mbps operation. Refer to
Section 3.0, “Functional
Collision Detected. The LXT971A asserts this output when a
collision is detected. This output remains High for the duration of the
collision. This signal is asynchronous and is inactive during full-
duplex operation.
Carrier Sense. During half-duplex operation (Register bit 0.8 = 0),
the LXT971A asserts this output when either transmitting or
receiving data packets. During full-duplex operation (Register bit 0.8
= 1), CRS is asserted only during receive. CRS assertion is
asynchronous with respect to RX_CLK. CRS is de-asserted on loss
of carrier, synchronous to RX_CLK.
Data Interface Pins
Signal Description
Description”.
“Clock Requirements” on page 26
Rev. Date: August 7, 2002
Document #: 249414
Revision #: 002
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