FLLXT971A Intel, FLLXT971A Datasheet - Page 70

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

www.DataSheet4U.com
DataSheet U .com
4
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
70
Figure 40. Power-Up Timing
Table 39. Power-Up Timing Parameters
Figure 41. RESET Pulse Width and Recovery Timing
Table 40. RESET Pulse Width and Recovery Timing Parameters
Voltage threshold
Power Up delay
RESET pulse width
RESET recovery delay
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance -
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
testing.
the PHY comes out of reset after a delay of No MORE Than 300 µ s. System designers should consider this
as a minimum value - After threshold v1 is reached, the MAC should delay No LESS Than 300 µ s before
accessing the MDIO port.
testing.
performance - the PHY comes out of reset after a delay of No MORE Than 300 µ s. System designers
should consider this as a minimum value - After de-asserting RESET*, the MAC should delay No LESS
Than 300 µ s before accessing the MDIO port.
MDIO,etc
MDIO,etc
Parameter
RESET
Parameter
VCC
2
2
Symbol
Symbol
v1
t1
t1
t2
Min
–
–
Min
10
–
v1
Typ
Typ
2.9
–
–
1
1
Max
Max
300
300
–
–
t1
Units
Units
µ s
ns
µ s
t1
V
Rev. Date: August 7, 2002
t2
Test Conditions
Test Conditions
Document #: 249414
Revision #: 002
–
–
Datasheet
–
–