FLLXT971A Intel, FLLXT971A Datasheet - Page 81

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 52. Configuration Register (Address 16, Hex 10)
16.4:3
16.15
16.14
16.13
16.12
16.10
1. R/W = Read /Write
2. The default value of Register bit 16.6 is determined by the state of the SLEEP pin 32/H7.
3. The default value of Register bit 16.0 is determined by pin 26/G2 (SD/TP).
16.11
16.9
16.8
16.7
16.6
16.5
16.2
16.1
16.0
Bit
LHR = Latches High on Reset
Reserved
Force Link Pass
Transmit Disable
Bypass Scrambler
(100BASE-TX)
Reserved
Jabber
(10BASE-T)
SQE
(10BASE-T)
TP Loopback
(10BASE-T)
CRS Select
(10BASE-T)
Sleep Mode
PRE_EN
Sleep Timer
Fault Code
Alternate NP
feature
Fiber Select
Enable
Name
Write as zero, ignore on read.
1 = Force Link pass
0 = Normal operation
1 = Disable Twisted Pair transmitter
0 = Normal Operation
1 = Bypass Scrambler and Descrambler
0 = Normal Operation
Ignore
1 = Disable Jabber Correction
0 = Normal operation
1 = Enable Heart Beat
0 = Disable Heart Beat
1 = Disable TP loopback during half-duplex
operation
0 = Normal Operation
1 = CRS deassert extends to RX_DV deassert
0 = Normal Operation
1 = Enable Sleep Mode
0 = Disable Sleep Mode
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when
CRS is asserted.
00 = 3.04 seconds
01 = 2.00 seconds
10 = 1.04 seconds
1 = Enable FEFI transmission
0 = Disable FEFI transmission
1 = Enable alternate auto negotiate next page
feature.
0 = Disable alternate auto negotiate next page
feature
1 = Select fiber mode.
0 = Select TP mode.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
Default
Note 2
Note 3
00
0
0
0
0
0
0
0
0
1
0
1
0
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