FLLXT971A Intel, FLLXT971A Datasheet - Page 18

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
18
Table 4.
LXT971A Miscellaneous Signal Descriptions
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
B7, C7
PBGA
Pin#
G1
D1
D2
C2
F1
F2
E2
E1
H1
H8
H7
E8
B1
C1
D7
LQFP
9, 10
Pin#
16
15
14
13
12
17
33
32
39
44
5
6
4
1
2
REFCLK/XI
PWRDWN
TxSLEW0
TxSLEW1
Symbol
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
RESET
PAUSE
SLEEP
RBIAS
N/C
XO
Type
AI
O
-
I
I
I
I
I
I
I
I
I
I
I
1
Tx Output Slew Controls 0 and 1. These pins select the TX
output slew rate (rise and fall time) as follows:
Reset. This active Low input is OR’ed with the control
register Reset bit (Register bit 0.15). The LXT971A reset
cycle is extended to 258 µs (nominal) after reset is de-
asserted.
Address <4:0>. Sets device address.
Bias. This pin provides bias current for the internal circuitry.
Must be tied to ground through a 22.1 k
Pause. When set High, the LXT971A advertises Pause
capabilities during auto-negotiation.
Sleep. When set High, this pin enables the LXT971A to go
into a low-power sleep mode. The value of this pin can be
overridden by Register bit 16.6 when in managed mode.
Power Down. When set High, this pin puts the LXT971A in a
power-down mode.
Crystal Input and Output. A 25 MHz crystal oscillator circuit
can be connected across XI and XO. A clock can also be
used at XI. Refer to
Functional Description section.
No Connection. These pins are not used and should not be
terminated.
TxSLEW1
0
0
1
1
TxSLEW0
“Clock Requirements” on page 26
Signal Description
0
1
0
1
Slew Rate (Rise and Fall Time)
Rev. Date: August 7, 2002
Ω
, 1% resistor.
3.0 ns
3.4 ns
3.9 ns
4.4 ns
Document #: 249414
Revision #: 002
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