FLLXT971A Intel, FLLXT971A Datasheet - Page 79

• Manufacturer Part Number: FLLXT971A
• Description: 3.3V Dual Speed Fast Ethernet PHY Transceicer
• Manufacturer: Intel

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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 49. Auto-Negotiation Expansion (Address 6)
Table 50. Auto-Negotiation Next Page Transmit Register (Address 7)
1. RO = Read Only LH = Latching High
1. RO = Read Only. R/W = Read/Write
7.10:0
6.15:6
7.15
7.14
7.13
7.12
7.11
6.5
6.4
6.3
6.2
6.1
6.0
Bit
Bit
Reserved
Base Page
Parallel
Detection Fault
Link Partner
Next Page Able
Next Page Able
Page Received
Link Partner A/N
Able
Next Page
(NP)
Reserved
Message Page
(MP)
Acknowledge 2
(ACK2)
Toggle
(T)
Message/Unformatted
Code Field
Name
Name
Ignore on read.
This bit indicates the status of the auto-negotiation
variable base page. It flags synchronization with the
auto-negotiation state diagram, allowing detection of
interrupted links. This bit is only used if Register bit
16.1 (Alternate NP feature) is set.
1 = Base page = true
0 = Base page = false
1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred.
1 = Link partner is next page able.
0 = Link partner is not next page able.
1 = Local device is next page able.
0 = Local device is not next page able.
1 = Indicates that a new page has been received and
the received code word has been loaded into Register
5 (Base Pages) or Register 8 (Next Pages) as specified
in Clause 28 of IEEE 802.3. This bit is cleared on Read.
If Register bit 16.1 is set, the Page Received bit is also
cleared when mr_page_rx = false or transmit_disable =
true.
1 = Link partner is auto-negotiation able.
0 = Link partner is not auto-negotiation able.
1 = Additional next pages follow
0 = Last page
Write as 0, ignore on read
1 = Message page
0 = Unformatted page
1 = Complies with message
0 = Cannot comply with message
1 = Previous value of the transmitted Link Code
Word equalled logic zero
0 = Previous value of the transmitted Link Code
Word equalled logic one
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Description
Description
Type
R/W
R/W
R/W
R/W
R/W
Type
RO
RO/
RO/
RO
RO
RO
RO
RO
LH
LH
LH
1
1
00000000
Default
Default
001
0
0
1
0
0
0
0
0
0
1
0
0
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