LMX2355SLB National Semiconductor, LMX2355SLB Datasheet - Page 13

• Manufacturer Part Number: LMX2355SLB
• Description: PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer
• Manufacturer: National Semiconductor

Programming Description
3.0 INPUT DATA REGISTER
The descriptions below describe the 24-bit data register loaded through the MICROWIRE Interface. The data register is used to
program the 15-bit IF_R counter register, and the 15-bit RF_R counter register, the 15-bit IF_N counter register, and the 19-bit
RF_N counter register. The data format of the 24-bit data register is shown below. The control bits CTL [1:0] decode the internal
register address. On the rising edge of LE, data stored in the shift register is loaded into one of 4 appropriate latches (selected
by address bits). Data is shifted in MSB first
3.1 Register Location Truth Table
3.2 Register Content Truth Table
4.0 PROGRAMMABLE REFERENCE DIVIDERS
4.1 IF_R REGISTER
If the Control Bits (CTL [1:0]) are 0 0, when data is transferred from the 24-bit shift register into a latch when LE is transitioned
high. This register determines the IF R counter value, IF Charge pump current, FoLD pin output, fractonal modulus, and oscillator
mode.
4.1.1 OSC
The OSC bit, IF_R [23], selects whether the oscillator inputs OSC
a common input signal path. When OSC = 0 , the OSC
When the OSC = 1, the OSC
4.1.2 FRAC_16
The FRAC_16 bit, IF_R [22], is used to set the fractional compensation at either 1/16 and 1/15 resolution. When FRAC-16 is set
to one, the fractional modulus is set to 1/16 resolution, and FRAC_16 = 0 corresponds to 1/15 (See section 5.2.3).
RF_R DLL_MODE
RF_N
MSB
OSC
23
IF_R
IF_N
First Bit
OSC
23
RF_CTL_WORD
IF_CTL_WORD
FRAC_16
22
(IF_R[23])
MSB
23
FRAC_16
1
0
0
1
1
(IF_R[22])
V2_EN
22
FoLD [2:0]
21
IF
21 20 19
pin drives both R counters.
FoLD
RF_CP_WORD
CMOS OUTPUTS/
CTL [1:0]
FRAC TEST
IF_CP_WORD
18
DATA [21:0]
19 18
17
C_WORD
IF_CP_WORD [1:0]
IF
pin drives the IF R counter while the OSC
16 15 14 13 12 11 10
REGISTER BIT LOCATION
0
0
1
0
1
13
IF
and OSC
17 16
IF_NB_CNTR
RF
IF_R_CNTR [14:0]
drive the IF and RF R counters separately or by
B_WORD
9
RF_R_CNTR
IF_R_CNTR
DATA Location
IF_R register
IF_N register
RF_R register
RF_N register
8
2 1
A_WORD FRAC_CNTR
7
CTL [1:0]
RF
pin drives the RF R counter.
6 5
2 1
0
LSB
IF_NA_CNTR 0 1
4
0
3
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LSB
0
0
Last Bit
2
c1
1
0 0
1 0
1 1
c2
0