LMX2355SLB National Semiconductor, LMX2355SLB Datasheet - Page 3

• Manufacturer Part Number: LMX2355SLB
• Description: PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer
• Manufacturer: National Semiconductor

Pin No. for
Package
Pin Descriptions
TSSOP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
Pin No. for
Package
CSP
24
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
OUT0
V
V
CP
GND
fin RF
fin RF
GND
OSC
OSC
Fo/LD
RF_EN
IF_EN
CLOCK
DATA
LE
GND
fin IF
fin IF
GND
CPo
V
V
OUT1
CC RF
P RF
PIF
CC IF
Name
o RF
Pin
IF
RF
IF
I/O
—
—
—
—
—
—
—
—
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.
RF PLL power supply voltage input. Must be equal to Vcc
2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
Power supply for RF charge pump. Must be
RF charge pump output. Connected to a loop filter for driving the control input
of an external VCO.
Ground for RF PLL digital circuitry.
RF prescaler input. Small signal input from the VCO.
RF prescaler complimentary input. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
Ground for RF PLL analog circuitry.
Dual mode oscillator output or RF R counter input. Has a V
when configured as an input and can be driven from an external CMOS or TTL
logic gate.
Oscillator input which can be configured to drive both the IF and RF R counter
inputs or only the IF R counter depending on the state of the OSC
programming bit. (See functional description 1.1 and programming description
3.1.)
Multiplexed output of N or R divider and RF/IF lock detect. CMOS output. (See
programming description 3.1.5.)
RF PLL Enable. Powers down RF N and R counters, prescaler, and
TRI-STATE
RF PLL depending on the state of RF_CTL_WORD. (See functional description
1.9.)
IF PLL Enable. Powers down IF N and R counters, prescaler, and TRI-STATE
charge pump output when LOW. Bringing IF_EN high powers up IF PLL
depending on the state of IF_CTL_WORD. (See functional description 1.9.)
High impedance CMOS Clock input. Data for the various counters is clocked
into the 24-bit shift register on the rising edge.
Binary serial data input. Data entered MSB first. The last two bits are the
control bits. High impedance CMOS input.
Load Enable high impedance CMOS input. Data stored in the shift registers is
loaded into one of the 4 internal latches when LE goes HIGH. (See functional
description 1.7.)
Ground for IF analog circuitry.
IF prescaler complimentary input. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
IF prescaler input. Small signal input from the VCO.
Ground for IF digital circuitry.
IF charge pump output. For connection to a loop filter for driving the input of an
external VCO.
Power supply for IF charge pump. Must be
IF power supply voltage input. Must be equal to V
2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
Programmable CMOS output. Level of the output is controlled by IF_N [18] bit.
®
charge pump output when LOW. Bringing RF_EN high powers up
3
Description
V
V
CC RF
CC RF
CC RF
and V
and V
. Input may range from
IF
CC IF
CC IF
. May range from
CC
/2 input threshold
.
.
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