LMX2355SLB National Semiconductor, LMX2355SLB Datasheet - Page 17

• Manufacturer Part Number: LMX2355SLB
• Description: PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer
• Manufacturer: National Semiconductor

Programming Description
5.2 RF_N Register
If the control bits (CTL[2:0]) are 1 1, data is transferred from the 24-bit shift register into the RF_N register latch which sets the
RF PLL’s programmable N counter register and various control functions. The RF N counter consists of a 2-bit A counter, 2-bit B
counter, 11-bit C counter, and a 4-bit fractional counter. For proper operation, C_WORD^MAX{A_WORD, B_WORD}+2. Serial
data format is shown below.
5.2.1.1 RF_CTL_WORD
5.2.1.2 RF/IF Control Word Truth Table
The Counter Reset enable bit when activated allows the reset of both N and R counters. Upon powering up, the N counter
resumes counting in “close” alignment with the R counter (the maximum error is one prescaler cycle).
Activation of the PLL power down bits result in the disabling of the respective N counter divider and de-biasing of its respective
fin inputs (to a high impedance state). The respective R counter functionality also becomes disabled when the power down bit is
activated. The OSC
forces the respective charge pump and phase comparator logic to a TRI-STATE condition. The MICROWIRE control register
remains active and capable of loading and latching in data during all of the power down modes.
Both synchronous and asynchronous power down modes are available with the LMX235x family in order to adapt to different
types of applications. The power down mode bit IF_N[21] is used to select between synchronous and asynchronous power down.
The MICROWIRE control register remains active and capable of loading and latching in data during all of the power down modes.
Synchronous Power Down Mode
One of the PLL loops can be synchronously powered down by first setting the power down mode bit HIGH (IF_N[21] = 1) and then
asserting its power down bit (IF_N[22] or RF_N[22] = 1). The power down function is gated by the charge pump. Once the power
down bit is loaded, the part will go into power down mode upon the completion of a charge pump pulse event.
Asynchronous Power Down Mode
One of the PLL loops can be asynchronously powered down by first setting the power down mode bit LOW (IF_N[21] = 0) and
then asserting its power down bit (IF_N[22] or RF_N[22] = 1). The power down function is NOT gated by the charge pump. Once
the power down bit is loaded, the part will go into power down mode immediately.
Prescaler select is used to set the RF prescaler. The LMX2354 contains quadruple modulus prescalers. It uses the 16/17/20/21
prescaler mode to operate at 1.2 GHz–2.5 GHz. In addition, it can use the 8/9/12/13 prescaler to operate at 550 MHz–1.2 GHz.
MSB
RF_CTL_WORD
[2:0]
23
MSB
IF_CNT_RST/RF_CNT_RST
PWDN_IF/PWDN_RF
PWDN_MODE
PRESC_SEL
RF_CNT_RST
21 20
IF
C_WORD [10:0]
pin reverts to a high impedance state when both RF and IF power down bits are asserted. Power down
BIT
LMX2354
(RF_N[21]–RF_N[23])
10 9
B_WORD [1:0]
(Continued)
IF/RF counter reset
IF/RF power down
Power down mode
select
Prescaler Modulus
Select
PWDN_RF
FUNCTION
8
17
A_WORD [1:0]
7
Normal Operation
Powered up
Asynchronous power
down
8/9/12/13
0.5 GHz–1.2 GHz
6 5
FRAC_CONT [3:0]
0
PRESC_SEL
Reset
Powered down
Synchronous power
down
16/17/20/21
1.2 GHZ–2.5 GHZ
2 1
1
1
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LSB
LSB
1
0