LMX2355SLB National Semiconductor, LMX2355SLB Datasheet - Page 16

• Manufacturer Part Number: LMX2355SLB
• Description: PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer
• Manufacturer: National Semiconductor

www.national.com
Programming Description
5.1.2 CMOS (Programmable CMOS outputs)
Note: Test bit is reserved and should be set to zero for normal usage.
5.1.3 Programmable CMOS Output Truth Table
Test Bit IF_N[19] controls the fractional spur compensation and should be set to 0 for normal operation. If the test bit is set to 1,
then the fractional spurs become much worse, but the phase noise improves about 5 dB.
When the Fastlock bit is set to 1, OUT_0 and OUT_1 are don’t care bits. Fastlock mode utilizes the OUT0 and OUT1 output pins
to synchronously switch between active low and TRI-STATE. The OUT0 = LOW state occurs whenever the RF loop’s CP_8X is
selected HIGH while the Fastlock bit is set HIGH (see programming description 4.2.2). The OUT0 pin reverts to TRI-STATE when
the CP_8X bit is LOW. Similarly for the IF loop, the synchronous activation of OUT1 = LOW or TRI-STATE, is dependent on
whether the CP_GAIN_8 is high or low respectively (see programming description 4.1.4).
5.1.4 3-BIT IF SWALLOW COUNTER DIVIDE RATIO (IF A COUNTER)
Note: Swallow Counter Value: 0 to 7
5.1.5 12-BIT IF PROGRAMMABLE COUNTER DIVIDE RATIO (IF B COUNTER)
Note: Divide ratio: 3 to 4095 (Divide ratios less than 3 are prohibited)
MSB
Divide
Ratio
4095
3
4
•
IF_NB_CNTR
Minimum continuous count = 56 ( A=0, B=7)
IF_NB_CNTR
N divider continuous integer divide ratio 56 to 32,767.
Fastlock
OUT_0
OUT_1
Swallow Count
Test
Bit
FastLock
11
0
0
1
•
(A)
0
1
7
•
IF_NA_CNTR
IF_NA_CNTR
10
0
0
1
•
Location
IF_N[17]
IF_N[18]
IF_N[19]
IF_N[20]
9
0
0
1
•
8
0
0
1
•
TEST
(Continued)
2
0
0
1
•
OUT0 CMOS Output Pin
OUT1 CMOS Output Pin
Fastlock Mode Select
7
0
0
1
•
Fractional Test Bit
IF_NB_CNTR
(IF_N[17]–IF_N[20])
Function
Level Set
Level Set
16
6
0
0
1
•
IF_NA_CNTR
5
0
0
1
•
OUT_1
1
0
0
1
•
Normal Operation
CMOS Output
(IF_N[2]−IF_N[4])
4
0
0
1
•
LOW
LOW
0
(IF_N[5]–IF_N[16])
3
0
0
1
•
2
0
1
1
•
OUT_0
Fastlock Mode
Compensation
No Fractional
0
0
1
1
•
1
1
0
1
•
HIGH
HIGH
1
0
1
0
1
•
LSB