LMX2355SLB National Semiconductor, LMX2355SLB Datasheet - Page 20
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LMX2355SLB
Manufacturer Part Number
LMX2355SLB
Description
PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer
Manufacturer
National Semiconductor
Datasheet
1.LMX2355SLB.pdf
(23 pages)
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Programming Description
(Continued)
5.5 LOCK DETECT DIGITAL FILTER
The Lock Detect Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated
delay of approximately 15 ns. To enter the locked state (Lock = HIGH) the phase error must be less than the 15 ns RC delay for
5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately 30 ns. To exit the locked
state (Lock = LOW), the phase error must become greater than the 30 ns RC delay. When the PLL is in the power down mode,
Lock is forced LOW. A flow chart of the digital filter is shown at right.
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