87C196JV Intel Corporation, 87C196JV Datasheet - Page 32

• Manufacturer Part Number: 87C196JV
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

87C196KR, JV, JT, JR, CA Microcontrollers — Automotive
6.0
6.1
32
Warning: This configuration will effectively strap the pin either high or low. DO NOT Configure as Open
Drain output “1”, or as an Input pin. This device is CMOS.
Design Considerations
87C196KR, JV, JT, JR, and CA Design Considerations
7. Port Functions. Some port pins have been removed. P5.7, P5.6, P5.5, P5.1, P6.2, P6.3, P1.4
1. EPA Timer RESET/Write Conflict
2. Valid Time Matches
3. P6 PIN.4-.7 Not Updated Immediately
4. Write Cycle during Reset
5. Indirect Shift Instruction
6. P2.7 (CLKOUT)
7. CLKOUT
through P1.7, P2.3, P2.5, P0.0 and P0.1. The PxREG, PxSSEL, and PxIO registers can still be
updated and read. The programmer should not use the corresponding bits associated with the
removed port pins to conditionally branch in software. Treat these bits as RESERVED.
Additionally, these port pins should be setup internally by software as follows:
If the user writes to the EPA timer at the same time that the timer is reset, it is indeterminate
which will take precedence. Users should not write to a timer if using EPA signals to reset it.
The timer must increment/decrement to the compare value for a match to occur. A match does
not occur if the timer is loaded with a value equal to an EPA compare value. Matches also do
not occur if a timer is reset and 0 is the EPA compare value.
Values written to P6 REG are temporarily held in a buffer. If P6 MODE is cleared, the buffer
is loaded into P6 REG.x. If P6 MODE is set, the value stays in the buffer and is loaded into P6
REG.x when P6 MODE.x is cleared. Since reading P6 REG returns the current value in P6.
REG and not the buffer, changes to P6 REG cannot be read until/unless P6 MODE.x is
cleared.
If RESET occurs during a write cycle, the contents of the external memory device may be
corrupted.
The upper 3 bits of the byte register holding the shift count are not masked completely. If the
shift count register has the value 32 x n, where n = 1, 3, 5, or 7, the operand will be shifted 32
times. This should have resulted in no shift taking place.
P2.7 (CLKOUT) does not operate in open drain mode.
The CLKOUT signal is active on P2.7 during RESET for the KR, JV, JT, JR and CA devices.
b. Configured as Push/Pull, PxIO as “0”.
a. Written to PxREG as “1” or “0”.
c. Configured as LSIO.
Datasheet