87C196JV Intel Corporation, 87C196JV Datasheet - Page 5

• Manufacturer Part Number: 87C196JV
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

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Datasheet
Introduction
The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-
bit CPU.
The 87C196Kx and Jx family members are composed of the high-speed (16 MHz) core as well as
the following peripherals:
The 87C196KR, JV, JT, JR, and CA devices represent the fourth generation of MCS
microcontroller products implemented on Intel’s advanced 1 micron process technology. These
products are based on the 80C196KB device with improvements for automotive applications. The
instruction set is a true super set of 80C196KB. The 87C196JR, JT, and JV are 52-pin versions of
the 87C196KR device.
The 87C196JV and JT devices are memory scalars of the 87C196JR and are designed for strict
functional and electrical compatibility. The JT has 32 Kbytes of on-chip EPROM, 1.0 Kbytes of
Register RAM and 512 bytes of Code RAM. The JV has 48 Kbytes of on-chip EPROM, 1.5 Kbytes
of Register RAM and 512 bytes of Code RAM.
The 87C196CA device is a memory scalar of the 87C196KR in a 68-pin package with 32 Kbytes of
on-chip EPROM, 1.0 Kbytes of register RAM, and 256 bytes of code RAM. In addition, the CA
contains an extra peripheral for serial communications protocol CAN 2.0.
Table 1 summarizes the features of the 87C196Kx, Jx, and CA devices.
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Up to 48 Kbytes of Programmable EPROM
Up to 1.5 Kbytes of register RAM and 512 bytes of code RAM (16-bit addressing modes) with
the ability to execute from this RAM space
Up to eight channels–10-Bit/ ± 3 LSB analog to digital converter with programmable S/H
times with conversion times < 5 µs at 16 MHz
An asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud
rate generator
Interprocessor communication slave port
Synchronous serial I/O port with full duplex master/slave transceivers
A flexible timer/counter structure with prescaler, cascading, and quadrature capabilities
Up to ten modularized multiplexed high speed I/O for capture and compare (called Event
Processor Array) with 250 ns resolution and double buffered inputs
A sophisticated prioritized interrupt structure with programmable Peripheral Transaction
Server (PTS). The PTS has several channel modes, including single/burst block transfers from
any memory location to any memory location, a PWM and PWM toggle mode to be used in
conjunction with the EPA, and an A/D scan mode.
Serial communications protocol CAN 2.0 with 15 message objects of 8 bytes data length (CA
only)
Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers
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