87C196JV Intel Corporation, 87C196JV Datasheet - Page 7

• Manufacturer Part Number: 87C196JV
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
Datasheet
New Instructions
XCH/XCHB
Exchange the contents of two locations, either Word or Byte is supported.
BMOVi
Interruptable Block Move Instruction, allows the user to be interrupted during long executing
Block Moves.
TIJMP
Table Indirect JUMP. This instruction incorporates a way to do complex CASE level branches
through one instruction. An example of such code savings: several interrupt sources and only one
interrupt vector. The TIJMP instruction will sort through the sources and branch to the appropriate
sub-code level in one instruction. This instruction was added especially for the EPA structure, but
has other code saving advantages.
EPTS/DPTS
Enable and Disable PTS Interrupts (Works like EI and DI).
SFR Operation
An additional 256 bytes of SFR registers were added to the 8XC196Kx, Jx, and CA devices. These
locations were added to support the wide range of on-chip peripherals that these devices have. This
memory space (1F00–1FFFH) has the ability to be addressed as direct 8-bit addresses through the
“windowing” technique. Any 32-, 64- or 128-byte section can be relocated in the upper 32, 64 or
128 bytes of the internal register RAM (080–FFH) address space. The CA contains an additional
256 bytes of SFR registers for CAN functions located in memory space IE00-1EFFh.
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Total Utilization of ALL Available Pins (I/O Mux’d with Control)
Two 16-Bit Timers with Prescale, Cascading and Quadrature Counting Capabilities
Up to 12 Externally Triggered Interrupts
Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers
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