87C196JV Intel Corporation, 87C196JV Datasheet - Page 36

• Manufacturer Part Number: 87C196JV
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

87C196KR, JV, JT, JR, CA Microcontrollers — Automotive
6.2.1
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87C196CA Design Considerations
The 87C196CA device is a memory scalar of the 87C196KR device with integrated CAN 2.0. The
CA is designed for strict functional and electrical compatibility to the Kx family as well as
integration of on-chip networking capability. The 87C196CA has fewer peripheral functions than
the 196KR, due in part to the integration of the CAN peripheral. Following are the functionality
differences between the 196KR and 196CA devices.
196KR Features Unsupported on the 196CA:
9. EPA Channels 4 through 7
1. External Memory
2. Auto-Programming Mode
3. EPA4 through EPA7
4. Slave Port Support
5. Port Functions
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The JR C-step device is simply a 68-lead KR-C device packaged in a 52-lead package. The
reduced pin-out is achieved by not bonding-out the unsupported pins. EPA4–EPA7 are among
these pins that are not bonded-out. The fact that EPA4–EPA7 are still present allows the
programmer to use these channels as software timers, to start A/D conversions, reset timers,
etc. All of the port pin logic is still present and it is possible to use the EPA to toggle these pins
internally. Please refer to the 52-Lead Device section in this datasheet for further information.
On the JR D-step, the EPA4–EPA7 logic has NOT been removed from the device. This allows
the programmer to still use these channels (as on the C-step) for software timers, etc. The only
difference is that the associated port pin logic has been removed and does not exist internally.
To maintain C-step to D-step compatibility, programmers should make sure that their software
does not rely upon the removed pins.
Removal of the Buswidth pin means the bus cannot dynamically switch from 8- to 16-bit bus
mode or vice versa. The programmer must define the bus mode by setting the associated bits in
the CCB.
The 87C196CA device will ONLY support the 16-bit zero wait state bus during auto-
programming.
Since the CA device is based on the KR design, these functions are in the device, however
there are no associated pins. A programmer can use these as compare only channels or for
other functions like software timer, start an A/D conversion, or reset timers.
The Slave port can not be used on the 196CA due to a function change for P5.4/SLPINT and
P5.1/SLPCS not being bonded-out.
Some port pins have been removed. P5.1, P6.2, P6.3, P1.4 through P1.7, P2.3, P2.5, P0.0 and
P0.1. The PxREG, PxSSEL, and PxIO registers can still be updated and read. The programmer
should not use the corresponding bits associated with the removed port pins to conditionally
branch in software. Treat these bits as RESERVED.
Additionally, these port pins should be setup internally by software as follows:
Analog Channels 0 and 1
INST Pin Functionality
SLPINT and SLPCS Pin Support
HLD/HLDA Functionality
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External Clocking/Direction of Timer1
Quadrature Clocking Timer 1
Dynamic Buswidth
EPA Capture Channels 4–7
Datasheet