87C196JV Intel Corporation, 87C196JV Datasheet - Page 33

• Manufacturer Part Number: 87C196JV
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

6.2
Datasheet
87C196JR C-step to JR D-step – or – JV/JT A-step Design
Considerations
This section documents differences between the 87C197JV A-step (JV-A)/87C196JT A-step (JT-
A)/87C196JR D-step (JR-D) and the 87C196JR C-step/(JR-C). For a list of design considerations
between 68-lead and 52-lead devices, please refer to the 52-lead Device Design Considerations
section of this datasheet. Since the 87C196JV and JT are simply memory scalars of the 87C196JR,
the term ‘‘JR’’ in this section will refer to JV, JT, and JR versions of the device unless otherwise
noted.
The JR-C is simply a 87C196KR C-step (KR-C) device packaged within a 52-lead package. This
reduction in pin count necessitated not bonding-out certain pins of the KR-C device. The fact that
these “removed pins” were still present on the device but not available to the outside world allowed
the programmer to take advantage of some of the 68-lead KR features.
The JR-D is a fully-optimized 52-lead device based on the 87C196KR C-step device. The KR-C
design data base was used to assure that the JR-D would be fully compatible with the KR-C, JR-C
and other Kx family members. The main differences between the JR-D and the JR-C is that several
of the unused (not bonded-out) functions on the JR-C were removed altogether on the JR-D.
Following is a list of differences between the JR-C and the JR-D:
10. JV Additional Register RAM
8. EPA Overruns
9. Indirect Addressing with Auto-Increment
1. Port3 Push-Pull Operation
EPA “lock-up” can occur if overruns are not handled correctly, refer to Intel Techbit #DB0459
“Understanding EPA Capture Overruns”, dated 12-9-93. Applies to EPA channels with
interrupts and overruns enabled (ON/RT bit in EPA_CONTROL register set to “1”).
For the special case of a pointer pointing to itself using auto-increment, an incorrect access of
the incremented pointer address will occur instead of an access to the original pointer address.
All other indirect auto-increment accesses will note be affected. Please refer to Techbit
#MC0593.
Incorrect sequence:
Correct sequence:
The 8XC196JV has a total of 1.5 Kbytes of register RAM. The RAM is located in two
memory ranges: 0000h – 03FFh and 1C00h – 1DFFh.
It was discovered on JR-C that if Port3 is selected for push-pull operation (P34_DRV register)
during low speed I/O (LSIO), the port was driving data when the system bus was attempting to
input data. It is rather unlikely that this errata would affect an application because the
application would have to use Port3 for both LSIO and as an external addr/data bus.
Nonetheless, this errata was corrected on the JR-D.
ld ax,#ax
ldb bx,[ax]+
ld ax,#bx
ldb cx,[ax]+
Automotive — 87C196KR, JV, JT, JR, CA Microcontrollers
;
;
;
;
Results in ax being incremented by 1 and the contents of the address
pointed to by ax+1 to be loaded into bx.
where ax
to be loaded into bx and ax incremented by 1.
bx. Results in the contents of the address pointed to by ax
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