RB5C396 Ricoh Corporation, RB5C396 Datasheet
RB5C396
Related parts for RB5C396
RB5C396 Summary of contents
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... PC Card Controller compliant with PCMCIA 2.1/JEIDA 4.2 RF5C296/RF5C396L/RB5C396/RF5C396 APPLICATION MANUAL ELECTRONIC DEVICES DIVISION NO.EA-028-9804 ...
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The products and the product specifications described in this application manual are subject to change or dis- continuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to Ricoh sales ...
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... APPLICATIONS PIN CONFIGURATION (RF5C296) PIN ASSIGNMENTS (RF5C296) PIN CONFIGURATION (RF5C396L/RF5C396) PIN ASSIGNMENTS (RF5C396L/RF5C396) PIN CONFIGURATION (RB5C396) PIN ASSIGNMENTS (RB5C396) ...................................................................................... PIN DESCRIPTION ......................................................................................... 1. ISA Bus Interface ........................................................................................ 2. Card Slot Interface ........................................................................................ 3. Other Control Pins 4. Power and Ground Supply Pins ....................................................................................... BLOCK DIAGRAM FUNCTIONAL DESCRIPTION ......................................................................................... ...
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I/O Mapping ......................................................................................... 3. Memory Mapping ....................................................................................... 4. Expansion Function .................................................................................. 5. I/O Address Remapping 6. Summary of Internal Register HARDWARE DESIGN CONSIDERATIONS 1. Initial Value Setting Pins 2. Connections to System Bus 3. Connections to PCMCIA Slot ...
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... PCMCIA2.1 or JEIDA4.2 Standard. These controller LSIs can be used to configure an ISA bus system which supports PC cards. The RF5C296 supports one PC card slot while the RF5C396L, the RB5C396 and the RF5C396 support two PC card slots. Incorporating a buffer and a transceiver, each of these devices can be directly coupled to the ISA system bus and the PC card slots ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 • PACKAGES · RF5C296 144pin LQFP (t=1.7mm) · RF5C396L 208pin LQFP (t=1.7mm) 256pin PBGA (23 ´ 23) · RB5C396 · RF5C396 208pin QFP APPLICATIONS • PC (Notebook Type, Pen-based Type and Palm Top Type) • Docking Station • PDA • Handy Terminal 2 ...
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... SD1 ZEROWS# SD2 GND SD3 VCCAT SD4 SD5 IRQ9 SD6 SD7 140 POWERGOOD SPKROUT# INTR# RESETDRV 144 1 ) CD1# and CD2# are powered by VCC_AT * RF5C296/RF5C396L/RB5C396/RF5C396 100 90 80 VCC_AT VCC_AT VCC_CORE VCC_SLOT 10 20 GND SD15 CD2# 70 WP/IOIS16# CD10 CD2 CD9 CD1 CD8 CD0 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 PIN ASSIGNMENTS • RF5C296 Pin No. Symbol Pin No. 1 VCC5EN# 2 VPP_EN0 3 VPP_EN1 4 5VDET/GPI 5 RIOUT# 6 VCC3EN# 7 CS# 8 REG# 9 CD3 10 CD1# 11 CD4 12 CD11 13 CD5 14 CD12 15 CD6 16 INPACK# 17 CD13 18 VCCSLOT 19 CD7 20 GND 21 CD14 22 CE1# 23 CD15 24 CA10 25 CE2# 26 OE# 27 CA11 28 CIORD# 29 CA9 30 CIOWR# 31 CA8 32 CA17 ...
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... SD4 SD5 IRQ9 SD6 200 SD7 POWERGOOD SPKROUT# INTR# BVPP_EN1 BVPP_EN0 BVCC3EN# BVCC5EN# 208 CS ACD1# ,ACD2# ,BCD1#,BCD2# are powered by VCC_AT * RF5C296/RF5C396L/RB5C396/RF5C396 140 130 120 VCC_AT VCC_SLOT#1 VCC_CORE VCC_SLOT#0 VCC_SLOT 110 BCA22 104 BCA16 BCA21 BRDY/BSY# BCA20 100 BWE#/RGM# ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 PIN ASSIGNMENTS • RF5C396L/RF5C396 Pin No. Symbol Pin No. 1 AVPP_EN1 2 AVPP_EN0 3 A5VDET/AGPI 4 AVCC3EN# 5 AVCC5EN# 6 B5VDET/BGPI 7 RESETDRV 8 AREG# 9 ACD3 10 ACD1# 11 ACD4 12 ACD11 13 ACD5 14 ACD12 15 ACD6 16 ACD13 17 ACD7 18 ACD14 19 ACE1# 20 ACD15 21 ACA10 22 ACE2# 23 AOE# 24 VCCSLOT#0 25 ACA11 26 ACIORD# 27 VCC 28 ACA9 29 ACIOWR# 30 ACA8 31 GND 32 ACA17 ...
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... IRQ10 172 157 LA23 173 158 IOCS16# 174 159 SBHE# 175 160 MEMCS16# 176 ) I : Active “low” signals are indicated by “#”. * RF5C296/RF5C396L/RB5C396/RF5C396 Symbol Pin No. Symbol SA0 177 IRQ7 SA1 178 SA11 SYSCLK 179 SA12 SA2 180 REFRESH# SA3 181 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 PIN CONFIGURATION • RB5C396 PIN ASSIGNMENTS • RB5C396 Pin No. Symbol Pin No. A1 LA22 A2 LA21 A3 LA19 A4 LA17 A5 SD8 A6 SD11 A7 SD14 A8 BCD2# A9 BCD9 A10 BCD0 A11 BCA1 A12 BCA3 A13 BRESET A14 BCA25 A15 BCA23 A16 BCA16 ...
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... H8 F9 GND H9 F10 GND H10 F11 GND H11 F12 BWE# H12 F13 BCA9 H13 F14 BOE# H14 F15 BCA11 H15 F16 BCE2# H16 RF5C296/RF5C396L/RB5C396/RF5C396 Symbol Pin No. Symbol IRQ7 J1 SA16 SA11 J2 IOW# SA12 J3 IOR# SA9 J4 GND SA4 J5 GND GND J6 GND GND J7 GND ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 Pin No. Symbol Pin No. N1 IRQ9 N2 SD7 N3 SPKROUT# N4 B5VDET/BGPI N5 ACD3 N6 ACD13 N7 VCCSLOT#0 N8 VCC N9 GND N10 ACA21 N11 ARDY/BSY# N12 VCCSLOT#0 N13 ACA1 N14 AINPACK# N15 ACD1 N16 ACD0 10 Symbol Pin No. P1 POWERGOOD R1 P2 BVPP_EN1 R2 P3 A5VDET/AGPI R3 P4 AVCC3EN ACD5 R5 P6 ...
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... IRQ11, or IRQ15 may be used as system side DACK#, system side DREQ, and system side TC respectively in DMA mode Input Output, I/O : Input/Output, O (OD) : Open Drain Output, O (TS) : Tri-State Output Pin No. of the RB5C396 differ from those of others. Refer to “PIN CONFIGURATION”. * RF5C296/RF5C396L/RB5C396/RF5C396 Pin No. RF5C296 ...
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... Chip Select input. This signal is use for configura- CS# tion CS# control power down mode, in case of dri- ving by the I/O address Input Output, I/O : Input/Output, O (OD) : Open Drain Output, O (TS) : Tri-State Output Pin No. of the RB5C396 differ from those of others. Refer to “PIN CONFIGURATION” Function RF5C296 102 Pin No ...
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... I : Input Output, I/O : Input/Output, I/O (PD) : Input/Output with Pull-down Register, O (TS) : Tri-State Output All card slot interface signal names are pretended with A-(slot#0) and B-(slot#1). * For example, ACA25 to ACA0 are the card address buses to the slot#0. Pin No. of the RB5C396 differ from those of others. Refer to “PIN CONFIGURATION”. RF5C296/RF5C396L/RB5C396/RF5C396 Pin No. RF5C296 RF5C396* ...
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... All card slot interface signal names are pretended with A-(slot#0) and B-(slot#1). * For example, ACA25 to ACA0 are the card address buses to the slot #0. Pin No. of the RB5C396 differ from those of others. Refer to "PIN CONFIGURATION". 3) CD1# and CD2# are powered by VCC_AT instead of VCC_SLOT because hot plug-in/out is supported during card slot power is off. * ...
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... All card slot interface signal names are pretended with A-(slot#0) and B-(slot#1). * For example, ACA25 to ACA0 are the card address buses to the slot #0. Pin No. of the RB5C396 differ from those of others. Refer to “PIN CONFIGURATION”. 3) Applicable to only RF5C296. * RF5C296/RF5C396L/RB5C396/RF5C396 Pin No. ...
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... GND Ground Pin 1) All card slot interface signal names are pretended with A-(slot#0) and B-(slot#1). * For example, ACA25 to ACA0 are the card address buses to the slot#0. Pin No. of the RB5C396 differ from those of others. Refer to “PIN CONFIGURATION”. 16 Function RF5C296 91 76, 135 ...
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... LOGIC IOR#,IOW# MEMR#, MEMW# IOCS16# MEMCS16# ZEROWS#, IOCHRDY IRQn(DREQ, DACK#,TC) SYSCLK POWERGOOD RESETDRV SPKROUT# MISC. RI_OUT CONTROL INTR# 5VDET/GPI RF5C296/RF5C396L/RB5C396/RF5C396 ADDRESS BUFFER ADDRESS MAPPING LOGIC DATA BUS BUFFER CE1#, CE2# CARD CIORD#, CIOWR# STROBES OE#, WE#(TC#) REG#(DACK#) VPP_EN0 VPP_EN1 POWER CONTROL ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 FUNCTIONAL DESCRIPTION RF5C296 (RF5C396 controller for supporting one (two) card slot compliant to PCMCIA2.1/JEIDA4.2 68pin standard. Direct connection to the card slot is allowed due to the complete buffering of signals to the card. RF5C296/RF5C396 can also interface directly to the ISA bus. 1. Address Mapping Each socket has five independently enabled and controlled system memory address mapping windows and two independently enabled and controlled system I/O address mapping windows ...
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... RF5C296/RF5C396. Each of these power nets can be independently running at 3.3V or 5V. All of the voltage combinations listed on the next page are supported. RF5C296/RF5C396 can operate even with the single power supply 3.3V VCC_AT ISA bus ISA bus Interface RF5C296/RF5C396L/RB5C396/RF5C396 VCC_CORE VCC_SLOT#0 Slot#0 Interface Core Logic Slot#1 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 Core (VCC_CORE) 5V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V When 5VDET/GPI pin is connected to PCMCIA card slot pin #43 (VS1#) as shown in the figure, the following should be considered. (1) Interface Status Register bit7* (2) Card Detect and Control Register bit2* RF5C296/RF5C396 1) Refer to page 27 “INTERNAL RESISTERS” shown in the above table, the RF5C296 and the RF5C396 allow sharing of a power supply between their VCC_SLOTs and the * PCcard slots, provided that the VCC_CORE should be set to 3 ...
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... On 8bit host systems, the SBHE# input must be pulled high (inactive) for proper operation. The following is a truth table of the card enable logic. 16bit Window SBHE# YES L YES L YES H YES RF5C296/RF5C396L/RB5C396/RF5C396 A0 CE2 CE1# ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 6. Internal Register Access All of the control registers of the RF5C296/RF5C396 are 8bit width registers and can be accessed using an indi- rect indexing scheme. Only two I/O addresses such as (3E1h) and (3E0h) are used to access all control registers. RF5C296/RF5C396 has the external decode mode. In this mode, I/O address is decoded outside and input to CS#. When RESETDRV falls, if the level of INTR# pin is “ ...
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... Five or More Slots More than five PC card slots can also be supported through external decoding of the A15 to A1 pin signals for input to the CS# pin and thereby setting of any given I/O addresses of the internal registers for the RF5C296 and the RF5C396. RF5C296/RF5C396L/RB5C396/RF5C396 Device bit 0 0 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 8. PCMCIA-ATA Mode RF5C296/RF5C396 supports a PCMCIA-ATA interface mode. The following table shows the card interface sig- nals when PCMCIA-ATA mode is configured. PCMCIA I/O PIN No. Interface Signal 1 GND 2 CD3 3 CD4 4 CD5 5 CD6 6 CD7 7 CE1# 8 CA10 9 OE# 10 CA11 11 CA9 12 CA8 13 CA13 14 CA14 15 WE# 16 IREQ# ...
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... DMA transfer between memory in the I/O card and the I/O port via the system data bus. Only one slot at a time should be enabled for DMA transfer. And DMA transfer to/from DMA capable PC Card may 16bit as shown in the bus sizing table of page 21. RF5C296/RF5C396L/RB5C396/RF5C396 Mode Control Register 1 (Index=1Fh) bit5 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 The TC# (terminal count) pin signal input to the PC card becomes active low for output from the OE# pin at a cycle for reading from the PC card (a cycle for writing to the memory) and from the E# pin at a cycle for writing to the PC card (a cycle for reading from the memory). Further, the output REG# pin signal is always held at high level during DMA transfer ...
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... PC card is the I/O card. bit4 : Memory Write Protect. Indicates the state of the WP pin. Memory write accesses to the slot will not be blocked unless the Write Protect bit in the Card Memory Offset Address Register High Byte is set to “1”. RF5C296/RF5C396L/RB5C396/RF5C396 Read only Interface I/O Only Memory Only Memory & ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 bit3 : Card Detect 2. This bit specifies reading back of the input CD2# pin signal in the inverted state. This bit will be set to “1” in the presence of the card in the slot when the IC core is connected to the external pull- up resistor because the CD2# pin is connected to the GND pin inside the card. ...
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... For I/O cards, bit is set to “1” if Ring Indicate Enable bit in the Interrupt and General Control Register is set to “0” and STSCHG#/RI# signal from I/O card has been pulled low. This bit reads “0” for I/O cards if the Ring Indicate Enable bit in the Interrupt and General Control Register is set to “1”. RF5C296/RF5C396L/RB5C396/RF5C396 bit0 of Mode VCC5EN# ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 The Card Status Change Register contains the status for sources of the card status change interrupt. These sources can be enabled to generate a card status change interrupt by setting the corresponding bit in the Card Status Change Interrupt Configuration Register. There are two ways to reset this register, (1) Read Card Status Change Register (2) Write back “ ...
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... Default value is “0”. If this bit is set to “0”, the falling edge of the control strobes OE# and WE# will be generated from the first falling edge of SYSCLK after the falling edge of MEMW# or MEMR# in the 16bit memory cycle. If this bit is set to “1”, the control strobes OE# and WE# will not be syn- chronously delayed by SYSCLK. RF5C296/RF5C396L/RB5C396/RF5C396 31 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 1.6 Global Control Register Index : 1Eh Default value : This register is not duplicated per slot. This register can be accessed from either Slot#0 or Slot1# in RF5C396. Consequently, access to indexes of 1Eh and 5Eh means access to the same register. bit7 to bit4 : Reserved bit3 : IRQ14 Pulse Mode Enable. Setting this bit to “1” and bit 1 (Level Mode Interrupt Enable) to “0” will enable the RF5C296/RF5C396 to support pulse-mode IRQ14 interrupt output ...
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... Memory Window 1 Enable Bit. If this Bit is set to “0”, a memory access within the Memory Window 1 will inhibit the card enable signal. bit0 : Memory Window 0 Enable Bit. If this Bit is set to “0”, a memory access within the Memory Window 0 will inhibit the card enable signal. RF5C296/RF5C396L/RB5C396/RF5C396 Read & Write 33 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 1.8 Interrupt and General Control Register Index : 03h Default value : 0000 0000b bit7 : Ring Indicate Enable. Setting this bit to “0” for I/O card, the STSCHG#/RI# signal from the I/O card is used as the status change signal STSCHG#. The current status of the signal is then available to the read from the Interface Status Register and this signal can be configured as a source for the card status change interrupt. Setting this bit to “ ...
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... For I/O cards, a card status change interrupt will be generated if the STSCHG#/RI# has been pulled “L” assuming Ring Indicate Enable Bit (bit7) in Interrupt and General Control Register is set to “0”. RF5C296/RF5C396L/RB5C396/RF5C396 Read & Write bit2 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 2. I/O Mapping 2.1 I/O Control Register Index : 07h bit7 : I/O Window 1 Waite State. If this bit is set to “1” or this wait state is set by the wait# signal which is common to 8 and 16bit, 16bit system accesses occur with 1 additional wait state(4 SYSCLK). bit6 : I/O Window 1 Zero Waite State. If this bit is set to “1”, 8bit system I/O accesses occur with zero additional wait states and ZEROWS# signal will be active. bit5 : I/O Window 1 IOCS16# Source. If this bit is set to “ ...
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... Index I/O Window 0 : 0Bh Default value : 0000 0000b Index I/O Window 1 : 0Fh I/O Window 0 Stop Address A15 to A8 bit7 : address 15 bit6 : address 14 bit5 : address 13 bit4 : address 12 bit3 : address 11 bit2 : address 10 bit1 : address 9 bit0 : address 8 RF5C296/RF5C396L/RB5C396/RF5C396 Read & Write Read & Write Read & Write 37 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 3. Memory Mapping 3.1 System Memory Address n Mapping Start Low Byte Register Index Index : Memory Window 0 Memory Window 1 10h Default value : 0000 0000b bit7 : address 19 bit6 : address 18 bit5 : address 17 bit4 : address 16 bit3 : address 15 bit2 : address 14 bit1 : address 13 bit0 : address 12 3.2 System Memory Address n Mapping Start High Byte Register Index ...
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... Wait State Bit 0 wait state bit 1 wait state bit bit5 : Reserved bit4 : Reserved bit3 : address 23 bit2 : address 22 bit1 : address 21 bit0 : address 20 RF5C296/RF5C396L/RB5C396/RF5C396 Memory Window 2 Memory Window 3 22h 2Ah Memory Window 2 Memory Window 3 23h 2Bh # of additional cycle 0 standard 16bit cycle 1 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 3.5 Card Memory Offset Address n Low Byte Register Index : Memory Window 1 Memory Window 0 14h Default value : 0000 0000b bit7 : offset address 19 bit6 : offset address 18 bit5 : offset address 17 bit4 : offset address 16 bit3 : offset address 15 bit2 : offset address 14 bit1 : offset address 13 bit0 : offset address 12 3 ...
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... Voltage Selection Bit. If bit4 of Power and RESETDRV Control Register is set to “1”, setting this bit to “1” will set VCC3EN# “L”. If bit4 of Power and RESETDRV Control Register setting this bit to “0” will set VCC5EN# “L”. Default value is “0”. RF5C296/RF5C396L/RB5C396/RF5C396 Read & Write Read & Write ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 5. I/O Address Remapping This function is available only in RF5C396. I/O offset address can be set in the following registers. Card I/O address is the summation result of system address and I/O offset address. 5.1 Card I/O Offset Address 0 Low Byte Register Index : 36h Default value : 0000 0000b bit7 : offset address 7 bit6 : offset address 6 ...
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... Power and RESETDRV Control Register. Input CD1#, CD2#, BVD1, BVD2, RDY/BSY#, WAIT#, WP, INPACK# CA[25 : 0], CD[15 : 0], CE1#, CE2#, CIORD#, CIOWR#, OE#, REG#, RESET, WE# Output RF5C296/RF5C396L/RB5C396/RF5C396 Read & Write Read Only Read & Write 43 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 6. Summary of Internal Register Slot#0 Slot#1 offset offset +00h +40h Identification and Revision +01h +41h Interface Status +02h +42h Power and RESETDRV Control +03h +43h Interrupt and General Control +04h +44h Card Status Change +05h +45h Card Status Change Interrupt Configuration ...
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... Card I/O Offset Address 1 High Byte +3Ah +7Ah Chip Identification +3Bh +7Bh Mode Control 3 ) Chip Identification Register bit7 is read back “0” from RF5C296, “1” from RF5C396. * RF5C296/RF5C396L/RB5C396/RF5C396 Register Name Default Value 7654 to 3210 0 000 0000 0 000 0000 0 000 0000 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 HARDWARE DESIGN CONSIDERATIONS 1. Initial Value Setting Pins For the RF5C296 and the RF5C396, the SPKROUT#, RI_OUT#, and INTR# pins function as output pins normally but as input pins whose input status determine internal settings during the time that the RESETDRV pin is held at high level as shown in the diagram below ...
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... SA15 to SA10 pins are all caused to transition to “L”. This is because the status of the CE# pin affects the Power Down Mode (specified by bit0 in the Global Control Register (Index : 1Eh)). When the Power Down Mode is not in use, therefore, the CE# pin should be held at “L”. RF5C296/RF5C396L/RB5C396/RF5C396 One clock pulse T21 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 Whether external decoding or internal decoding is used, note that an address for access to the I/O window (not an address to access to the internal registers) is determined by decoding the address signals output from the SA23 to SA16 pins to (0000 0000)b. 2.3 RESETDRV and POWERGOOD Pins For the RF5C296 and the RF5C396, reset operation is conditional upon the POWERGOOD pin held at “L”and the RESETDRV pin held at “ ...
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... Determination of the high-level duration of the ZEROWS# and IOCHRDY pin signals (For details, see “2.1 IOCS16#, MEMCS16#, ZEROWS#, and IOCHRDY Pins” in “2. Connections to System Bus”.) As long as the above purposes can be achieved, the SYSCLK pin signal may be available at a maximum frequency of 11MHz form. RF5C296/RF5C396L/RB5C396/RF5C396 49 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 3. Connections to PCMCIA Slot 3.1 Pull-up Resistor The Personal Computer Memory Card Industry Association (PCMCIA) standard requires that some types of pins should be pulled up on the PC card slots. Besides these pins,there are some pins which must be pulled up on the system side. They are listed in the table below. ...
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... VCC_SLOT#0 for the Card Slot#0, the VCC_SLOT#1 for the Card Slot#1, and the VCC_AT for the ISA bus interface). On the contrary, the 3.3V power supply for the IC core is available in combination with both the 3.3V and 5V peripheral power supplies. RF5C296/RF5C396L/RB5C396/RF5C396 VCC_CORE Core Logic ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 The RF5C296 and the RF5C396 are designed to have their power supply system controlled by four output pins : VCC3EN#, VCC5EN#, VPP_EN0, and VPP_EN1. Set the VCC3EN# pin to “0” by controlling the internal register in case of that the 3.3V is supplied to the power supply (VCC_SLOT) of the PC card slots. Set the VCC5EN# pin to “0” ...
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... PC card status change, resulting in many cases where circuit change cannot be confined to the single IRQn pin. IRQn1 IRQn2 Under the supply voltage of 3.3V, diode selection requires sufficient care to regulate a voltage drop to a small value. RF5C296/RF5C396L/RB5C396/RF5C396 IRQn Pull-down resistor on system side Notice 53 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 SOFTWARE DESIGN CONSIDERATIONS 1. Confirmation of Access to Internal Registers The RF5C296 and the RF5C396 contains about fifty 8bit internal registers. One of these internal registers, the Identification and Revision Register (Index : 00h), which is intended for only reading operation and fixed at 83h, is useful for confirming access to the other internal registers. ...
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... I/O addresses on the PC card bus. The Card I/O Offset Address n Low/High Byte Registers, which always default to “00h”, may be omitted from setting to ensure I/O address matching between the ISA bus and the PC card bus in the same manner as for the RF5C296. RF5C296/RF5C396L/RB5C396/RF5C396 I/O address on PC card bus 0000h aaaah ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 The RF5C396 provides I/O address mapping as shown in the figure below : • I/O Address Mapping by RF5C296 I/O address on ISA bus 0000h aaaah I/O WINDOW 0 bbbbh 03E0h 03E1h cccch I/O WINDOW 1 ddddh FFFFh The settings of the internal registers relating to I/O address window setting are shown in the table on the next page. For details on the individual internal registers, see “ ...
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... Mapping Stop High/Low Byte Registers. On the PC card bus, each memory address window equals to its equiva- lent on the ISA bus plus the setting of the Card Memory Offset Address n Low Byte Register (forming a two's com- plement number). RF5C296/RF5C396L/RB5C396/RF5C396 Window 0 09h : bit7 to 0 Index ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 Particularly, on the PC card bus, there are two types of memory available : the common memory and the attribute memory, which can be selected by the Card Memory Offset Address n High/Low Byte Registers. The common memory and the attribute memory are used mainly for ordinary access and for storage of such data as PC card information, respectively. During access to the attribute memory, the REG# pin signal is held at “ ...
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... Write Protect These bits can be used to specify write protection on memory. Index Reg Active These bits can be used to specify access to the attribute memory in the IC card when set to “1”. RF5C296/RF5C396L/RB5C396/RF5C396 Window 1 Window 2 19h : bit3 to 0 21h : bit3 to 0 18h : bit7 to 0 20h : bit7 to 0 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 Index MEMCS16# This bit can be used to specify the generation of the MEMCS16# pin signal through decoding the A23 to A17 pin signals and through decoding the A23 to A12 pin signals when set to “0” and “1”, respectively. Index Window Enable These bits can be used to specify rendering the applicable memory address window active when set to “1”. ...
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... Standard Cycle (3 SYSCLK Cycle) TS SYSCLK MEMR# MEMW# ZEROWS# IOCHRDY (2) Zero Wait State Cycle (2 SYSCLK Cycle) TS SYSCLK MEMR# MEMW# ZEROWS# IOCHRDY (3) One Wait State Cycle (4 SYSCLK Cycle) TS SYSCLK MEMR# MEMW# ZEROWS# IOCHRDY RF5C296/RF5C396L/RB5C396/RF5C396 TC1 TC1 TC1 TS 61 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 A two or three wait state memory access cycle can be implemented by adding the TC1 in the one wait state mem- ory access cycle of (3). The 16bit memory access cycle is identical to the 16bit I/O cycle in terms of the output tim- ing for the IOCHRDY pin signal except that the latter is unavailable in zero wait state form. ...
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... Detect Resume Enable Bit) to “1” in the Card Detect and General Control Register (Index : 16h) and then setting bit3 (Card Detect Enable Bit) to “1” in the Card Status Interrupt Configuration Register (Index : 05h). For details on these registers, see their respective description in “INTERNAL REGISTERS”. RF5C296/RF5C396L/RB5C396/RF5C396 63 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 • Output Destination Settings for Interrupts Derived from IREQ# bit3 bit2 • Output Destination Setting for Interrupts Derived from PC Card Status Change INTR# Enable bit bit7 ...
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... The internal registers contained in the RF5C296 and the RF5C396 are grouped according to their functions to facilitate such processes as interrupt processing. While the internal registers are described in detail under classifi- cation by function in “INTERNAL REGISTERS”, they are described briefly under classification by pin on the PC card slot in this section. RF5C296/RF5C396L/RB5C396/RF5C396 65 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 5.1 CD1# and CD2# Pins The CD1# and CD2# pins are grounded within the PC card and pulled up on the PC card slot. Both the CD1# and CD2# pins are caused to transition to “L” upon insertion of the PC card into the PC card slot. Note that some of the internal registers are designed to control the CD1# and CD2# pins upon occurrence of both the CD1# and CD2# status change and others upon occurrence of either the CD1# or CD2# status change ...
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... Interrupt and General Control Register (Index : 03h) : bit7 (Ring Indicate Enable Bit) This bit can be set to “1” to specify output of the RING INDICATE# signal to the RI_OUT# pin. RF5C296/RF5C396L/RB5C396/RF5C396 Battery voltage conditions Faulty battery voltage conditions requiring battery replacement and not guar- anteeing data retention ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 5.4 5VDET/GPI Pin The GPI pin, as its full name “general-purpose input pin” suggests, functions as an input pin for general purpose use. Further, it can also be connected to the VS1# pin on the PC card slot to detect the 5V PC card. (For details, see “3.2 5VDET/GPI and VS1# Pins” in “3. Connections to PCMCIA Slot” in “HARDWARE DESIGN CONSIDERA- TIONS” ...
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... Interface Status Register (Index : 01h) : bit6(PC card Power Active Bit) This bit an be used to indicate the status of power supply to the PC card slot and set to “0” and “1” to indicate the power-off state (in which both the VCC3VEN# and VCC5VEN# pins are held at high level) and the power- on state, respectively. RF5C296/RF5C396L/RB5C396/RF5C396 69 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 ABSOLUTE MAXIMUM RATINGS Symbol Item V Power Supply Voltage CC Vte Terminal Voltage Topr Operating Temperature Tstg Storage Temperature Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation above these absolute maximum ratings may cause degradation or permanent damage to the device ...
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... CC 1) SD15 to SD0, ZEROWS IRQn, CA25 to CA0, CD15 to CD0, CE1#, CE2#, CIORD#, CIOWR#, OE#, WE SPKROUT#, RI_OUT#, INTR#, GPI, VCC3EN#, VCC5EN#, VPP_EN0, VPP_EN1, REG#, RESET * 4) IOCS16#, MEMCS16#, IOCHRDY * 5) GPI * 6) CD15 to CD0 * 7) RESETDRV * RF5C296/RF5C396L/RB5C396/RF5C396 Measuring Condition MIN. 2.0 –0.3 2.4 I =–12mA OH 2.4 I =–8mA OH 2.4 I =–4mA ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 DC ELECTRICAL CHARACTERISTICS (Vcc=3.3V) Symbol Item “H” Input Voltage “L” Input Voltage IL “H” Output Voltage OH1 “H” Output Voltage OH2 “H” Output Voltage OH3 “L” Output Voltage OL1 “L” Output Voltage ...
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... T40 OE#, WE# valid from MEMR#, MEMW# with memory delay inhibit T32a OE#, WE# valid from MEMR#, MEMW# 16bit windows T32b OE#, WE# valid from MEMR#, MEMW active T38 T31 CE#, REG# valid from LA <23 : 17>, SA <16 : 0> RF5C296/RF5C396L/RB5C396/RF5C396 V =5V±10%(3.3V±0.3V)* CC Item , Ta=0 to 70˚C, CL=100pF 2 Limits Unit MIN ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 Symbol CE#, REG# invalid from LA <23 : 17>, SA <16 : 0> T39 CD <23 : 17> valid delay from SD <15 : 0> when I/O read T71 SD <15 : 0> hold from MEMR# T72 CD <15 : 0> active from LA <23 : 17>, SA <16 : 0> T73 CD <15 : 0> valid delay from SD <15 : 0> when I/O write T74 SD <15 : 0> setup time from falling edge of MEMW# T75 SD <15 : 0> hold time from MEMW# T76 1) This Timing assumes a load capacitance of 50pF. ...
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... LA(23,17) BALE SA(16,0) SBHE# SD(15,0) (READ DATA) SD(15,0) (WRITE DATA) MEMR#,MEMW# MEMCS16# IOCHRDY ZEROWS# WAIT# CADR(25,0) CD(15,0) (READ DATA) CD(15,0) (WRITE DATA) OE#,WE# CE1#,CE2#,REG# RF5C296/RF5C396L/RB5C396/RF5C396 Tck1 Tckh ADDRESS VALID T71 VALID T75 T76 DATA VALID T7a T35 T5a T6a,T6c T5b T21a T20 T17 T41 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 2. 8/16bit I/O Cycle Symbol LA <23 : 17> setup time from to BALE falling T1 BALE pulse width T2 AEN setup time to IOR#, IOW# T45 AEN hold time to IOR#, IOW# T46 LA <23 : 17>, SA <17 : 0> and SBHE setup time to IOR#, IOW# T7 IOCS16# hold time from SA <15 : 0> T12 IOCS16# active from LA <23 : 17> T5a IOCS16# active from SA <16 : 0> ...
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... In the above table, the parenthesized specifications apply when V * whether V =5V±10% or 3.3±0.3V. CC Setup time of data to falling edge of CIOWR# (tdsu) depends on setup time of address to IOW# of system (Stdsu). tdsu (min.)=Stdsu-30ns.m RF5C296/RF5C396L/RB5C396/RF5C396 Item =3.3±0.3V. Accordingly, the non-parenthesized specifications alone apply CC NOTE Limits Unit MIN ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 • 8/16bit I/O Cycle SYSCLK LA(23,17) BALE AEN SA(16,0) SBHE# SD(15,0) (READ DATA) SD(15,0) (WRITE DATA) IOR#,IOW# IOCS16# IOCHRDY ZEROWS# WAIT# CADR(25,0) CD(15,0) (READ DATA) CD(15,0) (WRITE DATA) CIORD#,CIOWR# CE1#,CE2#,REG# IOIS16# 78 Tck1 Tckh T1 T2 T45 ADDRESS VALID T71 VALID T75 DATA VALID T35 ...
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... T87 SD <7 : 0> read data hold time T88 CS# setup time T89 CS# hold time SYSCLK LA(23,17) BALE SA(16,0) SBHE# AEN IOW# IOR# SD7 to 0(WRITE) SD7 to 0(READ) CS# RF5C296/RF5C396L/RB5C396/RF5C396 V CC Item ADDRESS VALID T1 T80 ADDRESS VALID T82 T81 T83 T85 T84 T87 T86 T88 T89 =5V±10%(3.3V±0.3V),Ta=0 to 70˚C, CL=100pF ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 4. Interrupt, Ring Indicate Speaker Symbol T50 RI# to RI_OUT# delay, SPKR# to SPKROUT# delay T51 Card Status Change, INTR# valid delay T52 Card Status Change, IRQn valid delay T53 INTR# pulse width T54 IREQ# to IRQn delay 1) In the above table, the parenthesized specifications apply when V ...
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... Reset from POWERGOOD Symbol RESETDRV setup time to POWERGOOD T60 RESETDRV falling edge from rising edge POWERGOOD T61 POWERGOOD RESETDRV RF5C296/RF5C396L/RB5C396/RF5C396 V =5V±10%(3.3V±0.3V),Ta=0 to 70˚C, CL=100pF CC Item T60 T61 Limits Unit MAX. MIN. ns 200 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 6. DMA Read Cycle Timing Symbol T41 IOCHRDY inactive from WAIT# active T42 IOCHRDY active to WAIT# inactive T33 CIOWE# active from IOW# T38 IOW# inactive to rising edge of CIOWR#, TC (WE#) T74 SD <15 : 0> valid to CD <15 : 0> valid T91 DACK# (IRQ9) active to DMA cycle begin T92 ...
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... SD(15,0) IOR# IOCHRDY CIOWR#,WE# (high) REG# (DACK# to card) CE1#,CE2# CD(15,0) CIORD# WAIT# IRQ11 or IRQ15 (TC from system) OE# (TC to card) RF5C296/RF5C396L/RB5C396/RF5C396 V CC Item =3.3±0.3V. Accordingly, the non-parenthesized specifications alone apply whether CC T94 DATA VALID T71 T42 T41 DATA VALID T33 T95 =5V±10%(3.3V±0.3V Ta=0 to 70˚ ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 8. DMA Request Timing Symbol DMA request from card to system T97 INPACK#, SPKP#, or IOIS16# (DREQ or DREQ# from card) IRQ10 (DREQ to system) For the RF5C296 and the RF5C396, the relation between the Read/Write timings for the DATA and ADDRESS sig- nals and those for the CIOWR#, CIORD#, WE#, and OE# signals is not specified, and dependent on the input timings for the relevant signals from the system bus and on the internal delay time of the named signals ...
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... BUS SYSTEM ADDRESS CONTROL DATA SUPPORT ENVIRONMENT • Driver Soft Phoenix Technologies,Ltd.(U.S.A.) SystemSoft Corporation(U.S.A.) • Demonstration board Demonstration board for RF5C396 RF5C296/RF5C396L/RB5C396/RF5C396 ADDRESS CONTROL DATA RF5C296 RF5C396L RF5C396 PWR CTRL PhoenixCARD Manager Plus TM SystemSoft's Card Soft TM CARD SLOT POWER SWITCHING 85 ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 PACKAGE DIMENSIONS • RF5C296 144pin LQFP (LQFP-144-P1) • RF5C396L 208pin LQFP (LQFP-208-P1) 104 105 157 86 22±0.4 0.866±0.016 20typ. 0.787typ 108 1 109 144 30.0±0.4 1.181±0.016 28.0typ. 1.102typ 208 0.15±0.05 0.006±0.002 1.5 +0.2 –0.15 0min ...
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... RB5C396 256pin PBGA (BGA-256-P1) RF5C296/RF5C396L/RB5C396/RF5C396 23.0±0.4 0.906±0.016 19.5typ. (1.17) 0.768typ. (0.046) 4–C1.15 (2.13) (0.084 1.27±0.10 1.97±0.40 0.05±0.004 0.078±0.016 (1.27´15=19.05) (0.05´15=0.75) 1.53±0.20 0.060± ...
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... RF5C296/RF5C396L/RB5C396/RF5C396 • RF5C396 208pin QFP (QFP-208-P1) 105 156 88 30.0±0.4 1.181±0.016 28.0typ. 1.102typ. 104 157 208 0.15±0.15 0.006±0.002 +0.2 3.35 –0.16 0min. +0.008 0min. 0.132 –0.006 3.8max. 0.150max. mm Unit : inch ...
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... Himemuro-cho, Ikeda City, Osaka 563, JAPAN Phone 81-727-53-1111 Fax 81-727-53-6011 YOKOHAMA OFFICE (International Sales) 3-2-3, Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa 222, JAPAN Phone 81-45-477-1697 Fax 81-45-477-1694 •1695 RICOH CORPORATION ELECTRONIC DEVICES DIVISION SAN JOSE OFFICE 3001 Orchard Parkway, San Jose, CA 95134-2088, U.S.A. Phone 1-408-432-8800 Fax 1-408-432-8375 ...