RB5C396 Ricoh Corporation, RB5C396 Datasheet - Page 45

• Manufacturer Part Number: RB5C396
• Description: PC Card Controller Compliant With Pcmcia 2.1/jeida 4.2
• Manufacturer: Ricoh Corporation

4. Expansion Function
4.1 Mode Control Register 1
Index : 1Fh
bit7 : When set to “1”, this bit specifies disabling bit7 in the data bus for an I/O address of 377h or 3F7h (at read
bit6 : In PCMCIA-ATA mode, the value of this bit appears at CA25.
bit5 : In PCMCIA-ATA mode, the value of this bit appears at CA24.
bit4 : In PCMCIA-ATA mode, the value of this bit appears at CA23.
bit3 : In PCMCIA-ATA mode, the value of this bit appears at CA22.
bit2 : In PCMCIA-ATA mode, the value of this bit appears at CA21.
bit1 : In PCMCIA-ATA mode, if this bit is set to “1”, the SPKR# input works as an LED input and IRQ12 works as an
bit0 : PCMCIA-ATA mode bit. “1” selects PCMCIA-ATA mode and “0” selects PCMCIA mode. Default value is “0”.
4.2 Mode Control Register 2
Index : 2Fh
bit7 to bit6 : DMA Request Selection Bits. DREQ from PC Card is defined according to these 2 bits. Default values
bit5
bit4
bit3
bit2
bit1
bit0
time). When set to “0”, this bit specifies no such disabling. This bit defaults to “0” and can be set indepen-
dently of bit0.
open drain LED output. Default value is “0”.
: If this bit is set to “1”, DREQ is “L” active. If this bit is set to “0”, DREQ is “H” active. Default value is
: DMA Mode TC Selection Bit.
: Direct 5V/3.3V Switch Enable. If bit4 of Power and RESETDRV Control Register is set to “1”, setting
: Input Acknowledge Enable. If this bit is set to “1”, INPACK# pin function is enabled. If this bit is set to
: IREQ# Sense Selection Bit. If this bit is set to “0”, IREQ# is “L”active. If this bit is set to “1”, IREQ# is
: Voltage Selection Bit. If bit4 of Power and RESETDRV Control Register is set to “1”, setting this bit to
are “0”.
If this bit is set to “0”, IRQ11 works as TC. If this bit is set to “1”, IRQ15 works as TC.
“0”.
this bit to “1” will allow the status of 5VDET/GPI pin to select VCC3EN# or VCC5EN# independently of
bit0. Default value is “0”.
“0”, INPACK# is disabled. When the input INPACK# pin signal is active, I/O read data are output to the
system data bus only if the input INPACK# pin signal is held at “L”. Default value is “0”.
“H”active. Default value is “0”.
“1” will set VCC3EN# “L”. If bit4 of Power and RESETDRV Control Register setting this bit to “0” will
set VCC5EN# “L”. Default value is “0”.
Default value : 0000 0000b
Default value : 0000 0000b
bit 7
DREQ
bit 6
INPACK#
01
Read & Write
Read & Write
RF5C296/RF5C396L/RB5C396/RF5C396
SPKR#/LED#
10
IOIS16#
11
41