LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 12

• Manufacturer Part Number: LM3S2110-IQN20-A0
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Table of Contents
List of Registers
System Control .............................................................................................................................. 54
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Internal Memory ........................................................................................................................... 110
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
12
Device Identification 0 (DID0), offset 0x000 ....................................................................... 62
Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 64
LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 65
Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 66
Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 67
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 68
Reset Cause (RESC), offset 0x05C .................................................................................. 69
Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 70
XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 74
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 75
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 77
Device Identification 1 (DID1), offset 0x004 ....................................................................... 78
Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 80
Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 81
Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 83
Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 85
Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 87
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 88
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 90
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 92
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 94
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 96
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 98
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 100
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 102
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 104
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 106
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 107
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 109
Flash Memory Address (FMA), offset 0x000 .................................................................... 115
Flash Memory Data (FMD), offset 0x004 ......................................................................... 116
Flash Memory Control (FMC), offset 0x008 ..................................................................... 117
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 119
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 120
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 121
USec Reload (USECRL), offset 0x140 ............................................................................ 122
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 123
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 124
User Debug (USER_DBG), offset 0x1D0 ......................................................................... 125
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 126
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 127
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 128
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 129
Preliminary
November 29, 2007