LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 204
LM3S2110-IQN20-A0
Manufacturer Part Number
LM3S2110-IQN20-A0
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S2110-IQN20-A0.pdf
(485 pages)
- Current page: 204 of 485
- Download datasheet (5Mb)
General-Purpose Timers
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x034
Type R/W, reset 0x0000.FFFF
204
Reset
Reset
Type
Type
Bit/Field
31:16
15:0
R/W
RO
31
15
0
1
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
R/W
RO
30
14
0
1
reserved
TBMRL
Name
R/W
RO
29
13
0
1
R/W
RO
28
12
0
1
R/W
RO
Type
27
11
R/W
0
1
RO
R/W
RO
26
10
0
1
0xFFFF
0x0000
Reset
R/W
RO
25
0
9
1
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
R/W
RO
24
0
8
1
reserved
TBMRL
R/W
RO
23
0
7
1
R/W
RO
22
0
6
1
R/W
RO
21
0
5
1
R/W
RO
20
0
4
1
R/W
RO
19
0
3
1
November 29, 2007
R/W
RO
18
0
2
1
R/W
RO
17
0
1
1
R/W
RO
16
0
0
1
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