UPD75518 NEC, UPD75518 Datasheet - Page 59

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

(7) Procedure for changing the system clock and CPU clock
The procedure for changing the system clock and CPU clock is explained using Fig. 4-16.
1
2
3
4
Notes 1. 10.7 s (at 6.0 MHz) or 15.3 s (at 4.19 MHz)
Commercial
power
line voltage
f
f
X
XT
V
The generation of a RESET signal starts CPU operation at the lowest speed of the main system
clock
The PCC is rewritten for highest-speed operation after a time elapse which is sufficient for the voltage
on the V
The removal of commercial power is detected using, for example, an interrupt input (INT4 is useful),
then SCC.0 is set to operate with the subsystem clock. (In this case, the start of subsystem clock
generation must be confirmed beforehand.) After a time (32 machine cycles) required to switch to
the subsystem clock elapses, SCC.3 is set to terminate main system clock generation.
After detecting the input of commercial power by using an interrupt, SCC.3 is cleared to start main
system clock generation. After a time required for stable generation, SCC.0 is cleared to operate at
highest speed.
= 4.19 MHz
= 32.768 kHz
DD
RESET signal
System clock
2. 21.8 ms (at 6.0 MHz) or 31.3 ms (at 4.19 MHz)
pin voltage
CPU clock
Note 1
DD
ON
OFF
after a wait time
pin to be high enough for highest-speed operation.
Fig. 4-16 Changing the System Clock and CPU Clock
Note 2
Internal reset
operation
Wait (31.3 ms)
for stable oscillation.
15.3 s
f
X
0.95 s
f
X
122 s
f
XT
PD75518(A)
0.95 s
f
X
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