UPD75518 NEC, UPD75518 Datasheet - Page 96

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

Notes 1. When WUP = 0, IRQCSI0 is always set on the 9th rising edge of SCK0.
Serial clock
(SCK0)
Address
(A7 - A0)
Command
(C7 - C0)
Data
(D7 - D0)
Signal name
2. If the BUSY state is present, data transfer is started after the READY state is set.
When WUP = 1, IRQCSI0 is set on the 9th rising edge of SCK0 only if a received address matches the value of the slave address register (SVA).
Master
Master
Master
Master/
slave
Output
device
Synchronous clock for
outputting address/
command/data, ACK
signal, synchronous
BUSY signal, and so on.
Address/command/data
is output during first 8
clock cycles.
8-bit data transferred in
phase with SCK0 after
REL signal and CMD
signal output
8-bit data transferred in
phase with SCK0 after
only CMD signal is
output, with REL signal
not being output
8-bit data transferred in
phase with SCK0, with
neither REL signal nor
CMD signal being
output
Definition
SCK0
SB0
(SB1)
SCK0
SB0
(SB1)
SCK0
SB0
(SB1)
SCK0
SB0
(SB1)
REL
Table 4-10 Various Signals (2/2)
1
CMD
CMD
2
Timing chart
1
1
1
7
2
2
2
8
7
7
7
9
8
8
8
10
Execution of
instruction to
write data to SIO0
when CSIE0 = 1
(Transfer start
request)
Condition for
output
Note 2
IRQCSI0 is set (on
rising edge of 9th
clock)
Flag
operation
Note 1
Timing of signal
output on serial data
bus
Address of slave
device on serial bus
Directions and
messages to slave
device
Data processed by
slave or master
Meaning
of signal