UPD77111 NEC, UPD77111 Datasheet - Page 24

• Manufacturer Part Number: UPD77111
• Description: 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
• Manufacturer: NEC

4.2 Initializing PLL
Initialization takes 1024 clocks and it takes the PLL 100 s to be locked.
external pin ( PD77110) when the RESET pin is deasserted inactive (high level).
PLL, the internal memory contents and register status of the DSP are not retained.
PLL is not initialized).
5. FUNCTIONS OF BOOT-UP ROM
RAM by using the internal boot-up ROM.
5.1 Boot at Reset
depending on their bit pattern, determines the boot mode (self boot or host boot). After boot processing, processing
is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory.
the duration of 12 clocks after reset has been cleared (the clock is input from CLKIN).
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Initializing the PLL starts from the 1024th input clock after the RESET pin has been asserted active (low level).
After that, the DSP operates with the set value of the PLL specified by a mask option ( PD77111 or 77112) or an
After initializing the PLL, be sure to execute boot-up processing to re-initialize the internal RAM. To initialize the
If the RESET pin is deasserted inactive before the PLL initialization mode is set, the DSP is normally reset (the
PLL initialization
(internal status)
To rewrite the contents of the instruction memory on power application or from program, boot up the instruction
The PD77110 has a function to verify the contents of the internal instruction RAM in the boot-up ROM.
After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and,
The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for
Note This setting is used when the DSP must be reset to recover from the standby mode after reset boot has
Caution Do not deassert the RESET signal inactive in the PLL initialization mode and during PLL lock
P1
0
0
1
1
been executed once.
RESET
CLKIN
period.
P0
0
1
1
0
Does not execute boot but branches to address 0x200
Executes host boot and then branches to address 0x200.
Executes self boot and then branches to address 0x200.
Setting prohibited
Data Sheet U12801EJ4V0DS00
1
1024
PLL initialization
mode
Boot Mode
2048
PD77110, 77111, 77112
Note
.
Approx. 100
PLL lock time
s