UPD77111 NEC, UPD77111 Datasheet - Page 32

• Manufacturer Part Number: UPD77111
• Description: 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
• Manufacturer: NEC

8.3.1 Settings related to clock control
general-purpose I/O ports P2 and P3, and can be used as PLL setting pins only when it is so specified.
PLL2 becomes valid in the PLL initialization mode, the value of PLL0 through PLL2 must be fixed before the PLL
initialization mode is set.
8.3.2 WAKEUP function
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External pins PLL0 through PLL2 are used to set the multiple of the PLL. PLL0 and PLL1 are multiplexed with
The multiple must be an integer from 1 to 8.
<PLL2: PLL1: PLL0> 000 m = 1
The output division ratio is fixed to 1/1 and the halt division ratio is fixed to 1/8.
Where the PLL multiple is m, the relationship between each operation mode and operating clock is as follows:
For details on how to set the PLL multiple, refer to 4.2 Initializing PLL. Because the setting of PLL0 through
The option that makes CLKOUT pin output valid or invalid is fixed to “valid”.
The WAKEUP function of the PD77110 is fixed to “valid”.
Normal operation mode
HALT mode
STOP mode
001 m = 2
111 m = 8
Operation Mode
:
Data Sheet U12801EJ4V0DS00
m times external input clock
m/8 times external input clock
Stopped
Clock Supplied to DSP
PD77110, 77111, 77112