AN2320 Freescale Semiconductor / Motorola, AN2320 Datasheet
AN2320
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AN2320 Summary of contents
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... Freescale Semiconductor, Inc. Application Note AN2320/D Rev. 0.1, 8/2002 Interfacing the MCF5272 to a Standalone CAN Controller Lynne Kelly The Controller Area Network (CAN) protocol is a serial communications protocol developed in the early 1980’s by Robert Bosch GmbH for the automotive sector and is currently the in TECD Applications vehicle Local Area Network (LAN) standard in Europe ...
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Freescale Semiconductor, Inc. MCF5272 Microprocessor The reference design is based on the M5272C3 development board using a daughter card to provide the standalone CAN controller circuitry. This application note details the design process, starting with an overview of the MCF5272 ...
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Freescale Semiconductor, Inc. with four TDM ports, a software HDLC module, a QSPI module, and support for a 3 channel PWM. In addition, it retains the System Integration Module, the Chip-Select Module, the MAC and hardware divide unit, the General ...
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Freescale Semiconductor, Inc. CAN Transceiver Regarding the interface, this has been touched on before. Few standalone CAN controllers on the market today have non-multiplexed bus interfaces and none offer a glueless interface to the MCF5272 external bus. Design complexity and ...
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Freescale Semiconductor, Inc. +3.3V GND +5V MAX682 Charge Pump Figure 2. CAN Daughter-Card Circuitry 2.1 SPI Interface The MCF5272 QSPI module provides a glueless SPI interface to the 82C900’s synchronous serial channel (SSC). The QSPI and SSC hardware interfaces are ...
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Freescale Semiconductor, Inc. SPI Interface A = QSPI clock delay. Determines the length of delay from the assertion of the chip-select to a valid QSPI_CLK delay. Programmed in the QSPI delay register (QDLYR Delay after transfer. Determines the ...
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Freescale Semiconductor, Inc. Infineon has added an optional fifth signal, a ready signal (RDY), to the standard SPI interface. This is a handshake signal, which can be used to indicate when the serial interface can be accessed by the host. ...
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Freescale Semiconductor, Inc. Clocking READ ACCESS Serial Clk 8 CLKS 8 CLKS Data In Addr Data Out Data Name A CS active to SerialClk active B Address transfer to data byte transfer, read access C Data ...
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Freescale Semiconductor, Inc. where CLKIN is the system clock frequency (66 MHz here) and B represents the value in the baud field of the QMR register and lies between 1 and 255 baud rate of 6MBps would require ...
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Freescale Semiconductor, Inc. 82C900 Extended I/O Both the message-specific and the CAN node specific global interrupts are distributed among eight interrupt nodes, CAN interrupt nodes 0 – 7, via Message Configuration and Global Interrupt Node Pointer registers. Each node can ...
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Freescale Semiconductor, Inc. 3.1 Transmitting and Receiving over the MCF5272 QSPI Interface The QSPI module is a standard SPI interface with queuing capabilities. Using an 80-byte block of static RAM, the QSPI module can queue transfers without ...
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Freescale Semiconductor, Inc. Transmitting and Receiving over the MCF5272 QSPI Interface Point to Transmit RAM Point to Transmit RAM Set QAR to 0x00 to point to first queue entry in command Set QAR to 0x00 to point to first queue ...
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Freescale Semiconductor, Inc. Transmitting and Receiving over the MCF5272 QSPI Interface vary between the different accesses (for example, the minimum time for a read access can be three times as much as a write access), it may be desirable to ...
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Freescale Semiconductor, Inc. Transmitting and Receiving over the MCF5272 QSPI Interface MCF5272_WR_QSPI_QAR(imm, MCF5272_QSPI_QAR_Tx); /*Write 82C900 register address into Tx RAM via QDR indicating a write*/ MCF5272_WR_QSPI_QDR(imm,(uint8)(CanRegAddr|CanWriteMask)); /*Write data for 82C900 register into Transmit RAM via QDR*/ MCF5272_WR_QSPI_QDR(imm,Data); /*Set Wrap register ...
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Freescale Semiconductor, Inc. Accessing the 82C900 Register 3.2 Accessing the 82C900 Register The 82C900 register set is divided between the global control shell and the message buffer unit. The global control shell registers are known as the standalone shell registers, ...
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Freescale Semiconductor, Inc. 82C900 Initialisation MCF5272_WR_QSPI_QDR(imm,Data); MCF5272_WR_QSPI_QWR(imm,MCF5272_QSPI_QWR_SendByte); MCF5272_WR_QSPI_QDLYR(imm,MCF5272_QSPI_QDLYR_CanEnable); while (!(MCF5272_RD_QSPI_QIR(imm) & MCF5272_QSPI_QIR_QSPIFinish /*The upper 4 bits of the register address are passed.*/ void CAN_SetPageReg(uint8 PageNumber) { MCF5272_IMM *imm = mcf5272_get_immp(); MCF5272_WR_QSPI_QAR(imm,MCF5272_QSPI_QAR_Tx); /*Page register address. Can be accessed regardless ...
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Freescale Semiconductor, Inc. 82C900 Initialisation 15 0 Figure 7. Node A/B Control Registers (ACR/BCR)—Lower 16-bits Table 1. Node A/B Control Registers (ACR/BCR)—Lower 16-bits Field Descriptions Bits Name 15–8 — Reserved 7 CA Node used for CAN communication over the bus ...
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Freescale Semiconductor, Inc. CAN Transmit and Receive Tsync The CAN bit time, therefore, equates to period of the bit time quantum. The TSEG1, SJW, and TSEG2 fields in the bit timing register are used to define the different segments and ...
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Freescale Semiconductor, Inc. CAN Transmit and Receive valid or invalid, and to signal the update of a message. The configuration register determines which CAN node the message object is assigned to, defines the message identifier length and number of data ...
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Freescale Semiconductor, Inc. CAN Transmit and Receive __interrupt__ void ext_irq1_handler (void) { MCF5272_IMM *imm = mcf5272_get_immp(); printf("ext_irq1_handler\n"); /*Read received data and output over M5272C3 terminal uart*/ CAN_MsgObj_RxData(Msg1,8); /*Set Int1 IPL =6, for /Out1*/ MCF5272_WR_SIM_ICR1(imm,0xE8888888); /*Msg obj interrupt pending flag reset*/ ...
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Freescale Semiconductor, Inc. CAN Transmit and Receive /*Msg obj interrupt pending flag reset*/ QSPI_SendByte(CAN_MSG_CTRL + (Msg*0x20), 0xFD); /*Msg obj remote request flag reset*/ QSPI_SendByte(CAN_MSG_CTRL+ (Msg*0x20),0x7F); /*Msg obj transmission request flag reset*/ QSPI_SendByte(CAN_MSG_CTRL+1 + (Msg*0x20), 0xDF); /*Inhibit transmission for Tx or ...
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Freescale Semiconductor, Inc. CAN Transmit and Receive enables a message object to generate an interrupt on successful transmission or CAN_MsgObj_IntEnable reception of data. It selects the interrupt node pointer to be used which can then be routed to the external ...
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Freescale Semiconductor, Inc. Revision History CAN_MsgObjTx_Reset resets a message object after transmission and must be called anytime transmit data updated. void CAN_MsgObjTx_Reset(uint8 Msg) { /*Msg obj tagged invalid to allow update*/ QSPI_SendByte(CAN_MSG_CTRL + (Msg*0x20), 0x7F); /*Msg obj ...
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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 AN2320/D For More Information On This Product, Go to: www.freescale.com ...