AN2320 Freescale Semiconductor / Motorola, AN2320 Datasheet - Page 11

• Manufacturer Part Number: AN2320
• Description: Interfacing the MCF5272 to a Standalone CAN Controller
• Manufacturer: Freescale Semiconductor / Motorola

3.1
The QSPI module is a standard SPI interface with queuing capabilities. Using an 80-byte block of static
RAM, the QSPI module can queue up to 16 transfers without CPU intervention. The RAM is divided into
a receive data RAM which is the initial destination for all received data, a transmit data RAM which is a
buffer for all out-bound data, and a command RAM which holds command data for each QSPI command to
be executed (including which chip-select to activate, whether to enable delays, how many bits to transfer
etc.).
The RAM is organised as 16 entries where 1 byte of command data, 1 word of transmit data, and 1 word of
receive data comprise 1 queue entry. It cannot be accessed directly but must be accessed via the QSPI
address register (QAR) and the QSPI data register (QDR). A write to the QDR results in data being written
to the RAM entry specified by the address in the QAR and a read from the QDR results in the data stored
at the address specified by the QAR being written to the QDR. The address stored in the QAR automatically
increments after a read from or a write to the QDR.
QSPI operation is initiated by writing a queue of commands to the command RAM, writing transmit data
into transmit RAM, and then enabling the QSPI to begin transfer. The QSPI begins execution at the
command in the queue entry pointed to by a queue pointer and the transmit data at the same entry is
transmitted. Data that is simultaneously received is stored in this entry before the queue pointer is
incremented. When all commands are executed the QSPI finished flag is set and an interrupt can be
generated. Queue pointers can be used to begin or end transfer at any entry in the queue and to determine
which command was last completed.
The flowchart in Figure 5 outlines the process of sending a byte of data to and reading a byte of data from
the 82C900 CAN controller. This explains the initialisation and mechanics of the MCF5272 QSPI interface
only. Accessing the registers on the Infineon device, in particular the addressing, is described in detail in
Section 3.2, “Accessing the 82C900 Register.” The initialisation, the send byte, and the receive byte
software routines are also given. Refer to the MCF5272 user’s manual on the MCF5272 webpage for the
QSPI module register set and bit level detail.
MOTOROLA
Transmitting and Receiving over the MCF5272
QSPI Interface
Interfacing the MCF5272 to a Standalone CAN Controller
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Transmitting and Receiving over the MCF5272 QSPI Interface
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