AN2320 Freescale Semiconductor / Motorola, AN2320 Datasheet - Page 15

• Manufacturer Part Number: AN2320
• Description: Interfacing the MCF5272 to a Standalone CAN Controller
• Manufacturer: Freescale Semiconductor / Motorola

Accessing the 82C900 Register
3.2
The 82C900 register set is divided between the global control shell and the message buffer unit. The global
control shell registers are known as the standalone shell registers, and they control the initialisation process
after power-on or reset, provide status information to the CPU on message transfers or on any pending
transfer interrupts, and are responsible for condensing the 72 interrupt sources to 8 to be distributed among
the 8 available CAN interrupt nodes. The registers assigned to the message buffer unit are known as the
TwinCAN registers. These registers are used as buffers for the 32 message objects and also as managers of
the FIFO, to transfer messages between the nodes internally if the in-built gateway logic is being used, and
to provide interrupt requests for transmission or on reception of a message object. An overview of the
memory map is given below in Figure 6. For register-specific information refer to the Infineon 82C900
user’s manual,
http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/public_download.jsp?oid=16123&parent_oid=16899.
Accessing all registers on the memory map requires 11-bit addressing. Referring to Figure 4, the first byte
transmitted by the host during an access contains address information. All other transfers during the same
access are data transfers. Of the first byte transferred, only the lower seven bits are used to define the register
address. The eighth bit, A7, is used to indicate whether the access is a read or a write transfer. The upper
four bits of the register address are provided by the PAGE register in the standalone shell register set. The
PAGE register itself can be accessed at addresses xx7C
stored in the register.
The 82C900 register address is therefore split in two as illustrated by the code below. This highlights the
setting of the register address for a write access. The upper four bits of the address are written to the PAGE
register and the lower 7 bits are concatenated with the read or write command and transmitted over the SPI.
void QSPI_SendByte(uint16 CanRegAddr, uint8 Data)
{
/*Pass upper 4 bits of 82C900 register address to be accessed */
/*First byte to Tx over QSPI.
indicate a write operation*/
15
MCF5272_IMM *imm = mcf5272_get_immp();
CAN_SetPageReg((uint8)(CanRegAddr>>7));
MCF5272_WR_QSPI_QAR(imm, MCF5272_QSPI_QAR_Tx);
MCF5272_WR_QSPI_QDR(imm,(uint8)(CanRegAddr|CanWriteMask));
Accessing the 82C900 Register
+02C0
+06E0
+0000
+0080
+0200
+0300
+0320
Interfacing the MCF5272 to a Standalone CAN Controller
H
H
H
H
H
H
H
Freescale Semiconductor, Inc.
Standalone Registers
Reserved
TwinCAN Registers (CAN node & Control)
Reserved
TwinCAN Registers (Message Object 0)
TwinCAN Registers (Message Object 1)
TwinCAN Registers (Message Object 31)
For More Information On This Product,
Figure 6. 82C900 Register Map
Use lower 7 bits of address and force the 8
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H
or xxFC
H
and hence independently of the value
th
bit to 1 to
MOTOROLA