AN2320 Freescale Semiconductor / Motorola, AN2320 Datasheet - Page 6

• Manufacturer Part Number: AN2320
• Description: Interfacing the MCF5272 to a Standalone CAN Controller
• Manufacturer: Freescale Semiconductor / Motorola

SPI Interface
2.1.2
The 82C900 Synchronous Serial Channel (SSC) is an SPI-compatible serial interface, which can be used to
connect the CAN controller to an external host. Transfers can be single-read or single -write accesses
although the channel itself is optimised for multiple transfers to consecutive addresses. An example of a
consecutive read access and a consecutive write access is shown in Figure 4. When the chip select is
activated, the first byte transferred should always be an address byte. The address itself is 7 bits wide with
the 8
then all transfers following the address are data transfers. The SSC internally increments the register
addresses during the transfer. The chip-select signal must remain active for the duration.
The 82C900 SSC is configured internally for 8-bit data transfers with msb first. Clock polarity is set to
inactive high; clock phase is configured for data shift on the leading edge and data capture on the following
edge of the SPI clock. The MCF5272 is also fixed for msb-first transfer while the data transfer size, the clock
polarity, and clock phase are programmable as detailed in Section 2.1.1, “MCF5272 QSPI Module.”
Mode pins on the 82C900 are used to configure the interface, to choose between an 8-bit multiplexed bus
and the SSC, and to select master when no external host is used or slave when it is. In this design, the
MCF5272 is the external host acting as master in the system, and the mode input pins are set for the SSC
interface and slave operation.
The MCF5272 QSPI signals are connected to four control pins on the 82C900, the functions of which are
multiplexed by the mode inputs. When the SSC interface is used in slave mode, control pin 0 (the 82C900
chip-select) is configured as an input, control pin 1 is configured as a serial clock input, control pin 2 is
configured as a serial data input (Master Transmit Slave Receive), and control pin 3 is configured as a serial
data output (Master Receive Slave Transmit).
6
th
A = QSPI clock delay. Determines the length of delay from the assertion of the chip-select to a valid
B = Delay after transfer. Determines the length of delay after a serial transfer. Programmed in the QSPI
Clock polarity is set to 0 making the inactive state of QSPI_CLK to be logic level 0.
Clock phase is set to 1 to have data changed on the leading edge and captured on the following edge.
bit, A7, used to indicate whether the access is a read or a write. If a consecutive access is requested,
QSPI_CLK delay. Programmed in the QSPI delay register (QDLYR).
delay register (QDLYR).
82C900 Synchronous Serial Channel
Interfacing the MCF5272 to a Standalone CAN Controller
Figure 3. QSPI Clocking and Data Transfer Parameters
Freescale Semiconductor, Inc.
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