AN2320 Freescale Semiconductor / Motorola, AN2320 Datasheet - Page 12

• Manufacturer Part Number: AN2320
• Description: Interfacing the MCF5272 to a Standalone CAN Controller
• Manufacturer: Freescale Semiconductor / Motorola

Transmitting and Receiving over the MCF5272 QSPI Interface
The QSPI initialisation software in the example code is used to set up the baud rate, clock phase, clock
polarity, clock delay, and delay after transfer. It is also used here to set up the command RAM. All entries
in the command RAM have the programmable delays enabled. As the timing specifications of the 82C900
12
Set QAR to 0x00 to point to first queue entry in command
RAM
Set start queue pointer to the top of transmit RAM.
Set end queue pointer to 1 for Tx of 2 bytes
Set chip select inactive level to 1
Set SPE field in the QSPI delay register to enable
Poll the SPI finish flag in the QIR.
Set QAR to 0x00 to point to first queue entry in command
RAM
Set start queue pointer to the top of transmit RAM.
Set end queue pointer to 1 for Tx of 2 bytes
Set chip select inactive level to 1
Set SPE field in the QSPI delay register to enable
Poll the SPI finish flag in the QIR.
Write QDR with address of 82C900 register
Write QDR with data byte for 82C900 register
Write QDR with address of 82C900 register
Write QDR with data byte for 82C900 register
Set QSPI Wrap Register
Set QSPI Wrap Register
Load Transmit RAM via QDR
Load Transmit RAM via QDR
Point to Transmit RAM
Point to Transmit RAM
Poll for Completion
Poll for Completion
Figure 5. MCF5272 QSPI: Reading and Writing to the 82C900
Enable Transfer
Enable Transfer
Interfacing the MCF5272 to a Standalone CAN Controller
Freescale Semiconductor, Inc.
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5.5 Mbit/s baud rate, 8 bit data transfer
Data change on leading, capture on following
Clock idle high
Delay after transfer = 2 = 970ns
QSPI clock delay = 6 = 91ns
Clear QSPI finish, abort and write collision flags
Clear interrupts
Set QAR to 0x20 to point to first queue entry in command
RAM
8 bit data transfer
Use /CS0, assert between transfers
Enable programmable clock and transfer delays
5.5 Mbit/s baud rate, 8 bit data transfer
Data change on leading, capture on following
Clock idle high
Delay after transfer = 2 = 970ns
QSPI clock delay = 6 = 91ns
Clear QSPI finish, abort and write collision flags
Clear interrupts
Set QAR to 0x20 to point to first queue entry in command
RAM
8 bit data transfer
Use /CS0, assert between transfers
Enable programmable clock and transfer delays
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Write to Command RAM via QDR
Write to Command RAM via QDR
Clear QSPI Interrupt Register
Clear QSPI Interrupt Register
Set QSPI Delay Register
Point to Command RAM
Set QSPI Mode Register
Set QSPI Delay Register
Point to Command RAM
Set QSPI Mode Register
RD or WR?
RD or WR?
Set QAR to 0x00 to point to first queue entry in Tx RAM
Set start queue pointer to the top of transmit RAM.
Set end queue pointer to 1 for Tx of 2 bytes
Set chip select inactive level to 1
Set SPE field in the QSPI delay register to enable
Poll the SPI finish flag in the QIR.
Set QAR to 0x10 to point to first entry in Rx RAM.
Read dummy byte.
Read byte from 82C900 register access.
Set QAR to 0x00 to point to first queue entry in Tx RAM
Write QDR with address of 82C900 register
Write QDR with dummy addr for 82C900 register
Set start queue pointer to the top of transmit RAM.
Set end queue pointer to 1 for Tx of 2 bytes
Set chip select inactive level to 1
Set SPE field in the QSPI delay register to enable
Poll the SPI finish flag in the QIR.
Set QAR to 0x10 to point to first entry in Rx RAM.
Read dummy byte.
Read byte from 82C900 register access.
Write QDR with address of 82C900 register
Write QDR with dummy addr for 82C900 register
Set QSPI Wrap Register
Set QSPI Wrap Register
Load Transmit RAM via QDR
Load Transmit RAM via QDR
Read Receive RAM via QDR
Read Receive RAM via QDR
Point to Transmit RAM
Point to Transmit RAM
Point to Receive RAM
Point to Receive RAM
Poll for Completion
Poll for Completion
Enable Transfer
Enable Transfer
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