LM3S6633 Luminary Micro, Inc, LM3S6633 Datasheet - Page 9

• Manufacturer Part Number: LM3S6633
• Description: Lm3s6633 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10. Master Burst RECEIVE .................................................................................................. 383
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 384
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 385
Figure 15-13. Slave Command Sequence ............................................................................................ 386
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 18-1.
Figure 18-2.
Figure 21-1.
Figure 21-2.
Figure 21-3.
Figure 21-4.
Figure 21-5.
Figure 21-6.
Figure 21-7.
Figure 21-8.
Figure 21-9.
Figure 21-10. JTAG TRST Timing ........................................................................................................ 505
Figure 21-11. External Reset Timing (RST) .......................................................................................... 506
Figure 21-12. Power-On Reset Timing ................................................................................................. 507
Figure 21-13. Brown-Out Reset Timing ................................................................................................ 507
Figure 21-14. Software Reset Timing ................................................................................................... 507
Figure 21-15. Watchdog Reset Timing ................................................................................................. 507
Figure 22-1.
Figure 22-2.
July 25, 2008
START and STOP Conditions ......................................................................................... 376
Complete Data Transfer with a 7-Bit Address ................................................................... 377
R/S Bit in First Byte ........................................................................................................ 377
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 380
Master Single RECEIVE ................................................................................................. 381
Master Burst SEND ....................................................................................................... 382
Ethernet Controller Block Diagram .................................................................................. 411
Ethernet Controller ......................................................................................................... 411
Ethernet Frame ............................................................................................................. 413
Analog Comparator Module Block Diagram ..................................................................... 454
Structure of Comparator Unit .......................................................................................... 455
Comparator Internal Reference Structure ........................................................................ 456
100-Pin LQFP Package Pin Diagram .............................................................................. 465
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 466
Load Conditions ............................................................................................................ 496
I
External XTLP Oscillator Characteristics ......................................................................... 501
Hibernation Module Timing ............................................................................................. 502
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 503
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 503
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 504
JTAG Test Clock Input Timing ......................................................................................... 505
JTAG Test Access Port (TAP) Timing .............................................................................. 505
100-Pin LQFP Package .................................................................................................. 508
108-Ball BGA Package .................................................................................................. 510
2
C Timing ..................................................................................................................... 499
Preliminary
2
C Bus ............................................................... 377
LM3S6633 Microcontroller
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