LM3S2730 Luminary Micro, Inc, LM3S2730 Datasheet - Page 278

• Manufacturer Part Number: LM3S2730
• Description: Lm3s2730 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Synchronous Serial Interface (SSI)
12.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
278
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 12-4 on page 278 and Figure 12-5 on page 278.
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
Note:
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
In this configuration, during idle periods:
■
■
■
■
■
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
SSITx
SSIRx
SSITx
SSIRx
SSIClk is forced Low
SSIFss is forced High
The transmit data line SSITx is arbitrarily forced Low
When the SSI is configured as a master, it enables the SSIClk pad
When the SSI is configured as a slave, it disables the SSIClk pad
LSB
LSB
Q is undefined.
MSB
MSB
MSB
MSB
Preliminary
4 to 16 bits
4 to 16 bits
LSB
LSB
LSB
LSB
MSB
MSB
Q
July 25, 2008