LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 310

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
General-Purpose Timers
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
310
Bit/Field
31:11
7:4
10
RO
RO
9
8
3
2
1
0
31
15
0
0
RO
RO
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
30
14
0
0
reserved
RO
RO
TBTORIS
29
13
TATORIS
reserved
CBMRIS
reserved
CAMRIS
CBERIS
CAERIS
0
0
RTCRIS
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
CBERIS
RO
RO
26
10
0
0
CBMRIS
RO
RO
Reset
25
0x00
0
9
0
0x0
0
0
0
0
0
0
0
TBTORIS
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RTCRIS
RO
RO
19
0
3
0
CAERIS
RO
RO
18
0
2
0
CAMRIS
RO
RO
17
0
1
0
June 02, 2008
TATORIS
RO
RO
16
0
0
0