LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 496

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Univeral Serial Bus (USB) Controller
17.2.1.2 IN Transactions
496
When operating as a USB device, data for IN transactions is handled through the FIFOs attached
to transmit endpoints. The sizes of the FIFOs for endpoints 1 to 3 are determined by the
USBTXFIFOADD register. The maximum size of a data packet that may be placed in a transmit
endpoint’s FIFO for transmission is programmable and is determined by the value written to the
USBTXMAXPn register for that endpoint. The endpoint’s FIFO can also be configured to use
double-packet or single-packet buffering. When double-packet buffering is enabled, two data packets
can be buffered in the FIFO, which also requires that the FIFO is at least two packets in size. When
double-packet buffering is disabled, only one packet can be buffered, even if the packet size is less
than half the FIFO size. The USB controller also supports a special mode for bulk endpoints that
allows automatic splitting of a larger FIFO into multiple packets that are maximum packet size
transfers.
Note:
Single-Packet Buffering
If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint
(as set in the USBTXFIFOSZ register), only one packet can be buffered in the FIFO and single-packet
buffering is required. When each packet is completely loaded into the transmit FIFO, the TXRDY bit
in the USBTXCSRLn register needs to be set. If the AUTOSET bit in the USBTXCSRHn register is
set, the TXRDY bit is automatically set when a maximum sized packet is loaded into the FIFO. For
packet sizes less than the maximum, the TXRDY bit must be set manually. When the TXRDY bit is
set, either manually or automatically, the packet is ready to be sent. When the packet has been
successfully sent, both TXRDY and FIFONE are cleared and the appropriate transmit endpoint
interrupt signaled. At this point, the next packet can be loaded into the FIFO.
Double-Packet Buffering
If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint,
two packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is
loaded into the transmit FIFO, the TXRDY bit in in the USBTXCSRLn register needs to be set. If the
AUTOSET bit in the USBTXCSRHn register is set, the TXRDY bit is automatically set when a maximum
sized packet is loaded into the FIFO. For packet sizes less than the maximum, TXRDY must be set
manually. When the TXRDY bit is set, either manually or automatically, the packet is ready to be
sent. After the first packet is loaded, TXRDY is immediately cleared and an interrupt is generated.
A second packet can now be loaded into the transmit FIFO and TXRDY set again (either manually
or automatically if the packet is the maximum size). At this point, both packets are ready to be sent.
After each packet has been successfully sent, TXRDY is cleared and the appropriate transmit endpoint
interrupt signaled to indicate that another packet can now be loaded into the transmit FIFO. The
state of the FIFONE bit at this point indicates how many packets may be loaded. If the FIFONE bit
is set, then there is another packet in the FIFO and only one more packet can be loaded. If the
FIFONE bit is clear, then there are no packets in the FIFO and two more packets can be loaded.
Note:
Special Bulk Handling
The packets transferred in bulk operations are defined by the USB specification to be 8, 16, 32 or
64 bytes in size. For some system designs, however, it may be more convenient for the application
The maximum packet size set for any endpoint must not exceed the FIFO size. The
USBTXMAXPn register should not be written to while there is data in the FIFO as unexpected
results may occur.
Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the
USBTXDPKTBUFDIS register. This bit is set by default, so it must be cleared to enable
double-packet buffering.
Preliminary
June 02, 2008