LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 460

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Inter-Integrated Circuit (I
16.2.1
16.2.1.1 START and STOP Conditions
16.2.1.2 Data Format with 7-Bit Address
460
Figure 16-2. I
SDA
I
The I
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are high.
Every transaction on the I
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 460) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
The protocol of the I
A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and
a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus
is considered busy after a START condition and free after a STOP condition. See Figure
16-3 on page 460.
Figure 16-3. START and STOP Conditions
SDA
When operating in slave mode, two bits in the I2CRIS register indicate detection of start and stop
conditions on the bus; while two bits in the I2CSMIS register allow start and stop conditions to be
promoted to controller interrupts (when interrupts are enabled).
Data transfers follow the format shown in Figure 16-4 on page 461. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
SCL
SCL
2
C Bus Functional Overview
2
C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
I2CSCL
Stellaris TM
condition
START
2
C) Interface
2
I2CSDA
C Bus Configuration
2
R PUP
C bus defines two states to begin and end a transaction: START and STOP.
2
with I 2 C Interface
3rd Party Device
C bus is nine bits long, consisting of eight data bits and a single
SCL
R PUP
SDA
Preliminary
with I 2 C Interface
3rd Party Device
SCL
condition
STOP
SDA
I 2 C Bus
SDA
SCL
June 02, 2008
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