LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 492
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LM3S3739
Manufacturer Part Number
LM3S3739
Description
Lm3s3739 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S3739.pdf
(664 pages)
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Reset
Reset
Type
Type
Inter-Integrated Circuit (I
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x014
Type RO, reset 0x0000.0000
492
Bit/Field
31:3
RO
RO
2
1
0
31
15
0
0
RO
RO
Register 15: I
This register specifies whether an interrupt was signaled.
30
14
0
0
STARTMIS
STOPMIS
RO
RO
DATAMIS
29
13
reserved
0
0
Name
2
C) Interface
RO
RO
28
12
0
0
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
RO
RO
27
11
0
0
Type
RW
RW
RO
RO
RO
RO
26
10
0
0
reserved
RO
RO
Reset
25
0x00
0
9
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stop Condition Masked Interrupt Status
This bit specifies the interrupt state for stop condition detect (after
masking) of the I
otherwise, an interrupt has not been generated since the bit was last
cleared.
Start Condition Masked Interrupt Status
This bit specifies the interrupt state for start condition detect (after
masking) of the I
otherwise, an interrupt has not been generated since the bit was last
cleared.
Data Masked Interrupt Status
This bit specifies the interrupt state for data received and data requested
(after masking) of the I
otherwise, an interrupt has not been generated since the bit was last
cleared.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
2
2
C slave block. If set, an interrupt was signaled;
C slave block. If set, an interrupt was signaled;
RO
RO
21
0
5
0
2
C slave block. If set, an interrupt was signaled;
RO
RO
20
0
4
0
RO
RO
19
0
3
0
STOPMIS
RW
RO
18
0
2
0
STARTMIS
RW
RO
17
0
1
0
June 02, 2008
DATAMIS
RO
RO
16
0
0
0
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