LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 524

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Univeral Serial Bus (USB) Controller
USB FIFO Endpoint 0 (USBFIFO0)
Base 0x4005.0000
Offset 0x020
Type R/W, reset 0x0000.0000
524
Host
Device
Bit/Field
31:0
R/W
R/W
31
15
0
0
R/W
R/W
Register 12: USB FIFO Endpoint 0 (USBFIFO0), offset 0x020
Register 13: USB FIFO Endpoint 1 (USBFIFO1), offset 0x024
Register 14: USB FIFO Endpoint 2 (USBFIFO2), offset 0x028
Register 15: USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C
These 32-bit registers provide an address for CPU access to the FIFOs for each endpoint. Writing
to these addresses loads data into the Transmit FIFO for the corresponding endpoint. Reading from
these addresses unloads data from the Receive FIFO for the corresponding endpoint.
Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of
access is allowed provided the data accessed is contiguous. All transfers associated with one packet
must be of the same width so that the data is consistently byte-, word- or double-word-aligned.
However, the last transfer may contain fewer bytes than the previous transfers in order to complete
an odd-byte or odd-word transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support
either single-packet or double-packet buffering. Burst writing of multiple packets is not supported
as flags need to be set after each packet is written.
Following a STALL response or a transmit error on endpoint 1–3, the associated FIFO is completely
flushed.
30
14
0
0
R/W
R/W
29
13
EPDATA
0
0
Name
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
Type
R/W
R/W
R/W
26
10
0
0
R/W
R/W
Reset
25
0x00
0
9
0
Preliminary
R/W
R/W
24
0
8
0
EPDATA
EPDATA
Description
Endpoint Data
Writing to this register loads the data into the Transmit FIFO and reading
unloads data from the Receive FIFO.
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
June 02, 2008
R/W
R/W
16
0
0
0